{"history":[],"article":{"id":"64bd2682-e58f-467d-be0d-ed0aaa6e524c","title":"Peripheral Component Interconnect","slug":"peripheral-component-interconnect","content":":::summary\n![Three 5-volt 32-bit PCI expansion slots on a motherboard (PC bracket on left side)](https://upload.wikimedia.org/wikipedia/commons/6/67/PCI///Slots///Digon3.JPG)\n**Name:** PCI \n**Fullname:** PCI Local Bus \n**Invent -date:** June 22, 1992 \n**Invent -name:** [Intel](https://bliptext.com/articles/intel) \n**Replaces:** [ISA](https://bliptext.com/articles/industry-standard-architecture), E[ISA](https://bliptext.com/articles/industry-standard-architecture), [MCA](https://bliptext.com/articles/micro-channel-architecture), [VLB](https://bliptext.com/articles/vesa-local-bus) \n**Super -date:** 2004 \n**Super -name:** [AGP](https://bliptext.com/articles/accelerated-graphics-port) for graphics (1997), [PCI Express](https://bliptext.com/articles/pci-express) \n**Width:** 32 or 64 \n**Pin Count:** 124 [32-bit](https://bliptext.com/articles/32-bit-computing) \n**Speed:** [Half-duplex](https://bliptext.com/articles/half-duplex): · 133 [MB](https://bliptext.com/articles/megabyte)/s (32-bit at 33 MHz – the standard configuration) · 266 [MB](https://bliptext.com/articles/megabyte)/s (32-bit at 66 MHz) · 266 [MB](https://bliptext.com/articles/megabyte)/s (64-bit at 33 MHz) · 533 [MB](https://bliptext.com/articles/megabyte)/s (64-bit at 66 MHz) \n**Hotplug:** Optional \n:::\n\n# \n**Peripheral Component Interconnect** (**PCI**) is a [local](https://bliptext.com/articles/local-[bus](https://bliptext.com/articles/[computer](https://bliptext.com/articles/computer)-bus)) [computer](https://bliptext.com/articles/computer) [bus](https://bliptext.com/articles/[computer](https://bliptext.com/articles/computer)-bus) for attaching [hardware](https://bliptext.com/articles/[computer](https://bliptext.com/articles/computer)-hardware) devices in a [computer](https://bliptext.com/articles/computer) and is part of the **PCI** Local Bus standard.\nThe PCI bus supports the functions found on a [processor bus](https://bliptext.com/articles/system-bus) but in a standardized format that is independent of any given [processor](https://bliptext.com/articles/processor-computing)'s native bus.\nDevices connected to the PCI bus appear to a [bus master](https://bliptext.com/articles/bus-mastering) to be connected directly to its own bus and are assigned addresses in the processor's [address space](https://bliptext.com/articles/address-space).\nIt is a [parallel](https://bliptext.com/articles/parallel-communication) bus, [synchronous](https://bliptext.com/articles/synchronous-circuit) to a single [bus clock](https://bliptext.com/articles/clock-signal).\nAttached devices can take either the form of an [integrated circuit](https://bliptext.com/articles/integrated-circuit) fitted onto the [motherboard](https://bliptext.com/articles/motherboard) (called a planar device in the PCI specification) or an [expansion card](https://bliptext.com/articles/expansion-card) that fits into a slot.\nThe PCI Local Bus was first implemented in [IBM PC compatibles](https://bliptext.com/articles/ibm-pc-compatible), where it displaced the combination of several slow [Industry Standard Architecture](https://bliptext.com/articles/industry-standard-architecture) (ISA) slots and one fast [VESA Local Bus](https://bliptext.com/articles/vesa-local-bus) (VLB) slot as the bus configuration.\nIt has subsequently been adopted for other computer types.\nTypical PCI cards used in PCs include: [network cards](https://bliptext.com/articles/network-card), [sound cards](https://bliptext.com/articles/sound-card), [modems](https://bliptext.com/articles/modem), extra ports such as Universal Serial Bus ([USB](https://bliptext.com/articles/usb)) or [serial](https://bliptext.com/articles/serial-port), [TV tuner cards](https://bliptext.com/articles/tv-tuner-card) and [hard disk drive](https://bliptext.com/articles/hard-disk-drive) [host adapters](https://bliptext.com/articles/host-adapter).\nPCI [video cards](https://bliptext.com/articles/video-card) replaced ISA and VLB cards until rising [bandwidth](https://bliptext.com/articles/bandwidth-computing) needs outgrew the abilities of PCI.\nThe preferred interface for video cards then became [Accelerated Graphics Port](https://bliptext.com/articles/accelerated-graphics-port) (AGP), a superset of PCI, before giving way to PCI Express.\nThe first version of PCI found in retail desktop computers was a [32-bit](https://bliptext.com/articles/32-bit-computing) bus using a 33 MHz bus clock and 5 V signaling, although the PCI 1.0 standard provided for a [64-bit](https://bliptext.com/articles/64-bit-computing) variant as well.\nThese have one locating notch in the card.\nVersion 2.0 of the PCI standard introduced 3.3 V slots, physically distinguished by a flipped physical connector to prevent accidental insertion of 5 V cards.\nUniversal cards, which can operate on either voltage, have two notches.\nVersion 2.1 of the PCI standard introduced optional 66 MHz operation.\nA server-oriented variant of PCI, PCI Extended ([PCI-X](https://bliptext.com/articles/pci-x)) operated at frequencies up to 133 MHz for [PCI-X](https://bliptext.com/articles/pci-x) 1.0 and up to 533 MHz for [PCI-X](https://bliptext.com/articles/pci-x) 2.0.\nAn internal connector for laptop cards, called **Mini PCI**, was introduced in version 2.2 of the PCI specification.\nThe PCI bus was also adopted for an external laptop connector standard – the [CardBus](https://bliptext.com/articles/cardbus).\nThe first PCI specification was developed by [Intel](https://bliptext.com/articles/intel), but subsequent development of the standard became the responsibility of the PCI Special Interest Group ([PCI-SIG](https://bliptext.com/articles/pci-sig)).\nPCI and PCI-X sometimes are referred to as either Parallel PCI or Conventional PCI to distinguish them technologically from their more recent successor [PCI Express](https://bliptext.com/articles/pci-express), which adopted a [serial](https://bliptext.com/articles/serial-communication), lane-based architecture.\nPCI's heyday in the desktop computer market was approximately 1995 to 2005.\nPCI and PCI-X have become obsolete for most purposes and has largely disappeared from many other modern motherboards since 2013; however they are still common on some modern desktops for the purposes of [backward compatibility](https://bliptext.com/articles/backward-compatibility) and the relative low cost to produce.\nAnother common modern application of parallel PCI is in [industrial PCs](https://bliptext.com/articles/industrial-pc), where many specialized expansion cards, used here, never transitioned to PCI Express, just as with some ISA cards.\nMany kinds of devices formerly available on PCI expansion cards are now commonly integrated onto motherboards or available in USB and PCI Express versions.\n\n# History\nWork on PCI began at the [Intel Architecture Labs](https://bliptext.com/articles/intel-architecture-labs) (IAL, also Architecture Development Lab) c. 1990.\nA team of primarily IAL engineers defined the architecture and developed a proof of concept chipset and platform (Saturn) partnering with teams in the company's desktop PC systems and core logic product organizations.\nPCI was immediately put to use in servers, replacing [Micro Channel architecture](https://bliptext.com/articles/micro-channel-architecture) (MCA) and [Extended Industry Standard Architecture](https://bliptext.com/articles/extended-industry-standard-architecture) (EISA) as the server expansion bus of choice.\nIn mainstream PCs, PCI was slower to replace [VLB](https://bliptext.com/articles/vesa-local-bus), and did not gain significant market penetration until late 1994 in second-generation [Pentium](https://bliptext.com/articles/p5-microarchitecture) PCs.\nBy 1996, VLB was all but extinct, and manufacturers had adopted PCI even for [Intel 80486](https://bliptext.com/articles/intel-80486) (486) computers.\nEISA continued to be used alongside PCI through 2000.\n[Apple Computer](https://bliptext.com/articles/apple-computer) adopted PCI for professional [Power Macintosh](https://bliptext.com/articles/power-macintosh) computers (replacing [NuBus](https://bliptext.com/articles/nubus)) in mid-1995, and the consumer [Performa](https://bliptext.com/articles/macintosh-performa) product line (replacing LC [Processor Direct Slot](https://bliptext.com/articles/processor-direct-slot) (PDS)) in mid-1996.\nOutside the server market, the 64-bit version of plain PCI remained rare in practice though, although it was used for example by all [(post-iMac) G3](https://bliptext.com/articles/power-macintosh-g3) and [G4 Power Macintosh computers](https://bliptext.com/articles/power-mac-g4).\nLater revisions of PCI added new features and performance improvements, including a 66 [MHz](https://bliptext.com/articles/megahertz) 3.3 [V](https://bliptext.com/articles/volt) standard and 133 [MHz](https://bliptext.com/articles/megahertz) [PCI-X](https://bliptext.com/articles/pci-x), and the adaptation of PCI signaling to other form factors.\nBoth PCI-X 1.0b and PCI-X 2.0 are backward compatible with some PCI standards.\nThese revisions were used on server hardware but consumer PC hardware remained nearly all 32-bit, 33 MHz and 5 volt.\nThe PCI-SIG introduced the serial [PCI Express](https://bliptext.com/articles/pci-express) in c. 2004.\nSince then, motherboard manufacturers have included progressively fewer PCI slots in favor of the new standard.\nMany new motherboards do not provide PCI slots at all, as of late 2013.\n# [A typical 32-bit, 5 V-only PCI card, in this case, a SCSI adapter from Adaptec | upload.wikimedia.org/wikipedia/commons/d/d2/Adaptec///AHA-2940AU.png]\n# [A motherboard with two 32-bit PCI slots and two sizes of PCI Express slots | upload.wikimedia.org/wikipedia/commons/0/0c/PCI///und///PCIe///Slots.jpg]\n\n# Auto configuration\nPCI provides separate memory and [memory-mapped I/O](https://bliptext.com/articles/memory-mapped-i-o) port address spaces for the [x86](https://bliptext.com/articles/x86) processor family, [64](https://bliptext.com/articles/64-bit-computing) and [32 bits](https://bliptext.com/articles/32-bit-computing), respectively.\nAddresses in these [address spaces](https://bliptext.com/articles/address-space) are assigned by software.\nA third address space, called the [PCI Configuration Space](https://bliptext.com/articles/pci-configuration-space), which uses a fixed addressing scheme, allows software to determine the amount of memory and I/O address space needed by each device.\nEach device can request up to six areas of memory space or [input/output](https://bliptext.com/articles/input-output) (I/O) port space via its configuration space registers.\nIn a typical system, the [firmware](https://bliptext.com/articles/firmware) (or [operating system](https://bliptext.com/articles/operating-system)) queries all PCI buses at startup time (via [PCI Configuration Space](https://bliptext.com/articles/pci-configuration-space)) to find out what devices are present and what system resources (memory space, I/O space, interrupt lines, etc.) each needs.\nIt then allocates the resources and tells each device what its allocation is.\nThe PCI configuration space also contains a small amount of device type information, which helps an operating system choose device drivers for it, or at least to have a dialogue with a user about the system configuration.\nDevices may have an on-board [read-only memory](https://bliptext.com/articles/read-only-memory) (ROM) containing executable code for x86 or [PA-RISC](https://bliptext.com/articles/pa-risc) processors, an [Open Firmware](https://bliptext.com/articles/open-firmware) driver, or an [Option ROM](https://bliptext.com/articles/option-rom).\nThese are typically needed for devices used during system startup, before device drivers are loaded by the operating system.\nIn addition, there are PCI Latency Timers that are a mechanism for PCI Bus-Mastering devices to share the PCI bus fairly.\n\"Fair\" in this case means that devices will not use such a large portion of the available PCI bus bandwidth that other devices are not able to get needed work done.\nNote, this does not apply to PCI Express.\n\"How this works is that each PCI device that can operate in bus-master mode is required to implement a timer, called the Latency Timer, that limits the time that device can hold the PCI bus. The timer starts when the device gains bus ownership, and counts down at the rate of the PCI clock. When the counter reaches zero, the device is required to release the bus. If no other devices are waiting for bus ownership, it may simply grab the bus again and transfer more data.\"\n\n# Interrupts\nDevices are required to follow a protocol so that the [interrupt-request](https://bliptext.com/articles/interrupt-request) (IRQ) lines can be shared.\nThe PCI bus includes four interrupt lines, INTA# through INTD#, all of which are available to each device.\nUp to eight PCI devices share the same IRQ line (INTINA# through INTINH#) in [APIC](https://bliptext.com/articles/advanced-programmable-interrupt-controller)-enabled x86 systems.\nInterrupt lines are not wired in parallel as are the other PCI bus lines.\nThe positions of the interrupt lines rotate between slots, so what appears to one device as the INTA# line is INTB# to the next and INTC# to the one after that.\nSingle-function devices usually use their INTA# for interrupt signaling, so the device load is spread fairly evenly across the four available interrupt lines.\nThis alleviates a common problem with sharing interrupts.\nThe mapping of PCI interrupt lines onto system interrupt lines, through the PCI host bridge, is implementation-dependent.\nPlatform-specific [firmware](https://bliptext.com/articles/firmware) or operating system code is meant to know this, and set the \"interrupt line\" field in each device's configuration space indicating which IRQ it is connected to.\nPCI interrupt lines are [level-triggered](https://bliptext.com/articles/interrupt).\nThis was chosen over [edge-triggering](https://bliptext.com/articles/interrupt) to gain an advantage when servicing a shared interrupt line, and for robustness: edge-triggered interrupts are easy to miss.\nLater revisions of the PCI specification add support for [message-signaled interrupts](https://bliptext.com/articles/message-signaled-interrupts).\nIn this system, a device signals its need for service by performing a memory write, rather than by asserting a dedicated line.\nThis alleviates the problem of scarcity of interrupt lines.\nEven if interrupt vectors are still shared, it does not suffer the sharing problems of level-triggered interrupts.\nIt also resolves the routing problem, because the memory write is not unpredictably modified between device and host.\nFinally, because the message [signaling is in-band](https://bliptext.com/articles/in-band-signaling), it resolves some synchronization problems that can occur with posted writes and [out-of-band](https://bliptext.com/articles/out-of-band-data) interrupt lines.\n[PCI Express](https://bliptext.com/articles/pci-express) does not have physical interrupt lines at all.\nIt uses message-signaled interrupts exclusively.\n\n# Conventional hardware specifications\nThese specifications represent the most common version of PCI used in normal PCs:\nThe PCI specification also provides options for 3.3 V signaling, [64-bit](https://bliptext.com/articles/64-bit-computing) bus width, and 66 MHz clocking, but these are not commonly encountered outside of PCI-X support on server motherboards.\nThe PCI bus arbiter performs bus arbitration among multiple masters on the PCI bus.\nAny number of bus masters can reside on the PCI bus, as well as requests for the bus.\nOne pair of request and grant signals is dedicated to each bus master.\n# [Diagram showing the different key positions for 32-bit and 64-bit PCI cards | upload.wikimedia.org/wikipedia/commons/1/15/PCI///Keying.svg]\n\n## Card voltage and keying\nTypical PCI cards have either one or two key notches, depending on their signaling voltage.\nCards requiring 3.3 volts have a notch 56.21 mm from the card backplate; those requiring 5 volts have a notch 104.41 mm from the backplate.\nThis allows cards to be fitted only into slots with a voltage they support.\n\"Universal cards\" accepting either voltage have both key notches.\n# [A PCI-X Gigabit Ethernet expansion card with both 5 V and 3.3 V support notches, side B toward the camera | upload.wikimedia.org/wikipedia/commons/c/c5/Intelpromtserverpcixadapter1000mta342.jpg]\n\n## Connector pinout\nThe PCI connector is defined as having 62 contacts on each side of the [edge connector](https://bliptext.com/articles/edge-connector), but two or four of them are replaced by key notches, so a card has 60 or 58 contacts on each side.\nSide A refers to the 'solder side' and side B refers to the 'component side': if the card is held with the connector pointing down, a view of side A will have the backplate on the right, whereas a view of side B will have the backplate on the left.\nThe pinout of B and A sides are as follows, looking down into the motherboard connector (pins A1 and B1 are closest to backplate).\n64-bit PCI extends this by an additional 32 contacts on each side which provide AD[63:32], C/BE[7:4]#, the PAR64 parity signal, and a number of power and ground pins.\nMost lines are connected to each slot in parallel.\nThe exceptions are:\nNotes:\n\n## Mixing of 32-bit and 64-bit PCI cards in different width slots\nMost 32-bit PCI cards will function properly in 64-bit PCI-X slots, but the bus clock rate will be limited to the clock frequency of the slowest card, an inherent limitation of PCI's shared bus topology.\nFor example, when a PCI 2.3, 66-MHz peripheral is installed into a PCI-X bus capable of 133 MHz, the entire bus backplane will be limited to 66 MHz.\nTo get around this limitation, many motherboards have two or more PCI/PCI-X buses, with one bus intended for use with high-speed PCI-X peripherals, and the other bus intended for general-purpose peripherals.\nMany 64-bit PCI-X cards are designed to work in 32-bit mode if inserted in shorter 32-bit connectors, with some loss of performance.\nAn example of this is the Adaptec 29160 64-bit [SCSI](https://bliptext.com/articles/scsi) interface card.\nHowever, some 64-bit PCI-X cards do not work in standard 32-bit PCI slots.\nInstalling a 64-bit PCI-X card in a 32-bit slot will leave the 64-bit portion of the card edge connector not connected and overhanging.\nThis requires that there be no motherboard components positioned so as to mechanically obstruct the overhanging portion of the card edge connector.\n# [A semi-inserted PCI-X card in a 32-bit PCI slot, illustrating the need for the rightmost notch and the extra room on the motherboard to remain backward compatible | upload.wikimedia.org/wikipedia/commons/6/64/PCI-X///in///a///32-bit///slot.jpg]\n# [64-bit SCSI card working in a 32-bit PCI slot | upload.wikimedia.org/wikipedia/commons/e/ed/64bit///PCI///SCSI///card///in///a///32bit///PCI///slot.jpg]\n\n# Physical dimensions\nPCI brackets heights:\nPCI Card lengths (Standard Bracket & 3.3 V):\nPCI Card lengths (Low Profile Bracket & 3.3 V):\n\n## Mini PCI\n**Mini PCI** was added to PCI version 2.2 for use in [laptops](https://bliptext.com/articles/laptop) and some routers; it uses a 32-bit, 33 MHz bus with powered connections (3.3 V only; 5 V is limited to 100 mA) and support for [bus mastering](https://bliptext.com/articles/bus-mastering) and [DMA](https://bliptext.com/articles/direct-memory-access).\nThe standard size for Mini PCI cards is approximately a quarter of their full-sized counterparts.\nThere is no access to the card from outside the case, unlike desktop PCI cards with brackets carrying connectors.\nThis limits the kinds of functions a Mini PCI card can perform.\nMany Mini PCI devices were developed such as [Wi-Fi](https://bliptext.com/articles/wi-fi), [Fast Ethernet](https://bliptext.com/articles/fast-ethernet), [Bluetooth](https://bliptext.com/articles/bluetooth), [modems](https://bliptext.com/articles/modem) (often Win[modems](https://bliptext.com/articles/modem)), [sound cards](https://bliptext.com/articles/sound-card), [cryptographic accelerators](https://bliptext.com/articles/cryptographic-accelerator), [SCSI](https://bliptext.com/articles/scsi), [IDE](https://bliptext.com/articles/integrated-drive-electronics)–[ATA](https://bliptext.com/articles/at-attachment), S[ATA](https://bliptext.com/articles/at-attachment) controllers and combination cards.\nMini PCI cards can be used with regular PCI-equipped hardware, using Mini PCI-to-PCI converters.\nMini PCI has been superseded by the much narrower [PCI Express Mini Card](https://bliptext.com/articles/pci-express-mini-card)\n# [A Mini PCI slot | upload.wikimedia.org/wikipedia/commons/c/c6/Mini///PCI///slot///PNr%C2%B00344.jpg]\n# [Mini PCI Wi-Fi card Type IIIB | upload.wikimedia.org/wikipedia/commons/b/b8/MiniPCI///WiFi.jpg]\n# [PCI-to-MiniPCI converter Type III | upload.wikimedia.org/wikipedia/commons/b/b1/MiniPCI///PCI.jpg]\n# [MiniPCI and MiniPCI Express cards in comparison | upload.wikimedia.org/wikipedia/commons/d/d8/MiniPCI///and///MiniPCI///Express///cards.jpg]\n\n### Technical details of Mini PCI\nMini PCI cards have a 2 W maximum power consumption, which limits the functionality that can be implemented in this form factor.\nThey also are required to support the CLKRUN# PCI signal used to start and stop the PCI clock for power management purposes.\nThere are three card [form factors](https://bliptext.com/articles/computer-form-factor): Type I, Type II, and Type III cards.\nThe card connector used for each type include: Type I and II use a 100-pin stacking connector, while Type III uses a 124-pin edge connector, i.e. the connector for Types I and II differs from that for Type III, where the connector is on the edge of a card, like with a [SO-DIMM](https://bliptext.com/articles/so-dimm).\nThe additional 24 pins provide the extra signals required to route [I/O](https://bliptext.com/articles/input-output) back through the system connector (audio, [AC-Link](https://bliptext.com/articles/ac-97), [LAN](https://bliptext.com/articles/lan), phone-line interface).\nType II cards have RJ11 and RJ45 mounted connectors.\nThese cards must be located at the edge of the computer or docking station so that the RJ11 and RJ45 ports can be mounted for external access.\nMini PCI is distinct from 144-pin Micro PCI.\n\n# PCI bus transactions\nPCI bus traffic consists of a series of PCI bus transactions.\nEach transaction consists of an address phase followed by one or more data phases.\nThe direction of the data phases may be from initiator to target (write transaction) or vice versa (read transaction), but all of the data phases must be in the same direction.\nEither party may pause or halt the data phases at any point.\n(One common example is a low-performance PCI device that does not support [burst transactions](https://bliptext.com/articles/burst-mode-computing), and always halts a transaction after the first data phase.)\nAny PCI device may initiate a transaction.\nFirst, it must request permission from a PCI bus arbiter on the motherboard.\nThe arbiter grants permission to one of the requesting devices.\nThe initiator begins the address phase by broadcasting a 32-bit address plus a [4-bit](https://bliptext.com/articles/4-bit-computing) command code, then waits for a target to respond.\nAll other devices examine this address and one of them responds a few cycles later.\n64-bit addressing is done using a two-stage address phase.\nThe initiator broadcasts the low 32 address bits, accompanied by a special \"dual address cycle\" command code.\nDevices that do not support 64-bit addressing can simply not respond to that command code.\nThe next cycle, the initiator transmits the high 32 address bits, plus the real command code.\nThe transaction operates identically from that point on.\nTo ensure compatibility with 32-bit PCI devices, it is forbidden to use a dual address cycle if not necessary, i.e. if the high-order address bits are all zero.\nWhile the PCI bus transfers 32 bits per data phase, the initiator transmits 4 active-low byte enable signals indicating which [8-bit](https://bliptext.com/articles/8-bit-computing) bytes are to be considered significant.\nIn particular, a write must affect only the enabled bytes in the target PCI device.\nThey are of little importance for memory reads, but I/O reads might have side effects.\nThe PCI standard explicitly allows a data phase with no bytes enabled, which must behave as a no-op.\n\n## PCI address spaces\nPCI has three address spaces: memory, I/O address, and configuration.\nMemory addresses are 32 bits (optionally 64 bits) in size, support [caching](https://bliptext.com/articles/cache-computing) and can be burst transactions.\nI/O addresses are for compatibility with the Intel [x86 architecture](https://bliptext.com/articles/x86-architecture)'s I/O port address space.\nAlthough the PCI bus specification allows burst transactions in any address space, most devices only support it for memory addresses and not I/O.\nFinally, [PCI configuration space](https://bliptext.com/articles/pci-configuration-space) provides access to 256 bytes of special configuration registers per PCI device.\nEach PCI slot gets its own configuration space address range.\nThe registers are used to configure devices memory and I/O address ranges they should respond to from transaction initiators.\nWhen a computer is first turned on, all PCI devices respond only to their configuration space accesses.\nThe computer's BIOS scans for devices and assigns Memory and I/O address ranges to them.\nIf an address is not claimed by any device, the transaction initiator's address phase will time out causing the initiator to abort the operation.\nIn case of reads, it is customary to supply all-ones for the read data value (0xFFFFFFFF) in this case.\nPCI devices therefore generally attempt to avoid using the all-ones value in important status registers, so that such an error can be easily detected by software.\n\n## PCI command codes\nThere are 16 possible 4-bit command codes, and 12 of them are assigned.\nWith the exception of the unique dual address cycle, the least significant bit of the command code indicates whether the following data phases are a read (data sent from target to initiator) or a write (data sent from an initiator to target).\nPCI targets must examine the command code as well as the address and not respond to address phases that specify an unsupported command code.\nThe commands that refer to cache lines depend on the [PCI configuration space](https://bliptext.com/articles/pci-configuration-space) cache line size register being set up properly; they may not be used until that has been done.\n\n# PCI bus latency\nSoon after promulgation of the PCI specification, it was discovered that lengthy transactions by some devices, due to slow acknowledgments, long data bursts, or some combination, could cause [buffer underrun](https://bliptext.com/articles/buffer-underrun) or overrun in other devices.\nRecommendations on the timing of individual phases in Revision 2.0 were made mandatory in revision 2.1:\nAdditionally, as of revision 2.1, all initiators capable of bursting more than two data phases must implement a programmable latency timer.\nThe timer starts counting clock cycles when a transaction starts (initiator asserts FRAME#).\nIf the timer has expired and the arbiter has removed GNT#, then the initiator must terminate the transaction at the next legal opportunity.\nThis is usually the next data phase, but Memory Write and Invalidate transactions must continue to the end of the cache line.\n\n## Delayed transactions\nDevices unable to meet those timing restrictions must use a combination of [posted writes](https://bliptext.com/articles/) (for memory writes) and delayed transactions (for other writes and all reads).\nIn a delayed transaction, the target records the transaction (including the write data) internally and aborts (asserts STOP# rather than TRDY#) the first data phase.\nThe initiator must retry exactly the same transaction later.\nIn the interim, the target internally performs the transaction, and waits for the retried transaction.\nWhen the retried transaction is seen, the buffered result is delivered.\nA device may be the target of other transactions while completing one delayed transaction; it must remember the transaction type, address, byte selects and (if a write) data value, and only complete the correct transaction.\nIf the target has a limit on the number of delayed transactions that it can record internally (simple targets may impose a limit of 1), it will force those transactions to retry without recording them.\nThey will be dealt with when the current delayed transaction is completed.\nIf two initiators attempt the same transaction, a delayed transaction begun by one may have its result delivered to the other; this is harmless.\nA target abandons a delayed transaction when a retry succeeds in delivering the buffered result, the bus is reset, or when 215=32768 clock cycles (approximately 1 ms) elapse without seeing a retry.\nThe latter should never happen in normal operation, but it prevents a [deadlock](https://bliptext.com/articles/deadlock-computer-science) of the whole bus if one initiator is reset or malfunctions.\n\n# PCI bus bridges\nThe PCI standard permits multiple independent PCI buses to be connected by bus bridges that will forward operations on one bus to another when required.\nAlthough PCI tends not to use many bus bridges, [PCI Express](https://bliptext.com/articles/pci-express) systems use many PCI-to-PCI bridge usually called [PCI Express](https://bliptext.com/articles/pci-express) Root Port; each [PCI Express](https://bliptext.com/articles/pci-express) slot appears to be a separate bus, connected by a bridge to the others.\nThe PCI host bridge (usually [northbridge](https://bliptext.com/articles/northbridge-computing) in x86 platforms) interconnect between CPU, main memory and PCI bus.\n\n## Posted writes\nGenerally, when a bus bridge sees a transaction on one bus that must be forwarded to the other, the original transaction must wait until the forwarded transaction completes before a result is ready.\nOne notable exception occurs in the case of memory writes.\nHere, the bridge may record the write data internally (if it has room) and signal completion of the write before the forwarded write has completed.\nOr, indeed, before it has begun.\nSuch \"sent but not yet arrived\" writes are referred to as \"posted writes\", by analogy with a postal mail message.\nAlthough they offer great opportunity for performance gains, the rules governing what is permissible are somewhat intricate.\n\n## Combining, merging, and collapsing\nThe PCI standard permits bus bridges to convert multiple bus transactions into one larger transaction under certain situations.\nThis can improve the efficiency of the PCI bus.\n\n### Combining\nWrite transactions to consecutive addresses may be combined into a longer burst write, as long as the order of the accesses in the burst is the same as the order of the original writes.\nIt is permissible to insert extra data phases with all byte enables turned off if the writes are almost consecutive.\n\n### Merging\nMultiple writes to disjoint portions of the same word may be merged into a single write with multiple byte enables asserted.\nIn this case, writes that were presented to the bus bridge in a particular order are merged so they occur at the same time when forwarded.\n\n### Collapsing\nMultiple writes to the same byte or bytes may not be combined, for example, by performing only the second write and skipping the first write that was overwritten.\nThis is because the PCI specification permits writes to have side effects.\n\n# PCI bus signals\nPCI bus transactions are controlled by five main control signals, two driven by the initiator of a transaction (FRAME# and IRDY#), and three driven by the target (DEVSEL#, TRDY#, and STOP#).\nThere are two additional arbitration signals (REQ# and GNT#) that are used to obtain permission to initiate a transaction.\nAll are [active-low](https://bliptext.com/articles/active-low), meaning that the active or asserted state is a low [voltage](https://bliptext.com/articles/voltage).\nPull-up resistors on the motherboard ensure they will remain high (inactive or deasserted) if not driven by any device, but the PCI bus does not depend on the resistors to change the signal level; all devices drive the signals high for one cycle before [ceasing to drive](https://bliptext.com/articles/three-state-logic) the signals.\n\n## Signal timing\nAll PCI bus signals are sampled on the rising edge of the clock.\nSignals nominally change on the falling edge of the clock, giving each PCI device approximately one half a clock cycle to decide how to respond to the signals it observed on the rising edge, and one half a clock cycle to transmit its response to the other device.\nThe PCI bus requires that every time the device driving a PCI bus signal changes, one turnaround cycle must elapse between the time the one device stops driving the signal and the other device starts.\nWithout this, there might be a period when both devices were driving the signal, which would interfere with bus operation.\nThe combination of this turnaround cycle and the requirement to drive a control line high for one cycle before ceasing to drive it means that each of the main control lines must be high for a minimum of two cycles when changing owners.\nThe PCI bus protocol is designed so this is rarely a limitation; only in a few special cases (notably [fast back-to-back transactions](https://bliptext.com/articles/)) is it necessary to insert additional delay to meet this requirement.\n\n## Arbitration\nAny device on a PCI bus that is capable of acting as a [bus master](https://bliptext.com/articles/bus-master) may initiate a transaction with any other device.\nTo ensure that only one transaction is initiated at a time, each master must first wait for a bus grant signal, GNT#, from an arbiter located on the motherboard.\nEach device has a separate request line REQ# that requests the bus, but the arbiter may \"park\" the bus grant signal at any device if there are no current requests.\nThe arbiter may remove GNT# at any time.\nA device that loses GNT# may complete its current transaction, but may not start one (by asserting FRAME#) unless it observes GNT# asserted the cycle before it begins.\nThe arbiter may also provide GNT# at any time, including during another master's transaction.\nDuring a transaction, either FRAME# or IRDY# or both are asserted; when both are deasserted, the bus is idle.\nA device may initiate a transaction at any time that GNT# is asserted and the bus is idle.\n\n## Address phase\nA PCI bus transaction begins with an address phase.\nThe initiator (usually a [chipset](https://bliptext.com/articles/chipset)), seeing that it has GNT# and the bus is idle, drives the target address onto the AD[31:0] lines, the associated command (e.g. memory read, or I/O write) on the C/BE[3:0]# lines, and pulls FRAME# low.\nEach other device examines the address and command and decides whether to respond as the target by asserting DEVSEL#.\nA device must respond by asserting DEVSEL# within 3 cycles.\nDevices that promise to respond within 1 or 2 cycles are said to have \"fast DEVSEL\" or \"medium DEVSEL\", respectively.\n(Actually, the time to respond is 2.5 cycles, since PCI devices must transmit all signals half a cycle early so that they can be received three cycles later.)\nA device must [latch](https://bliptext.com/articles/latch-electronics) the address on the first cycle; the initiator is required to remove the address and command from the bus on the following cycle, even before receiving a DEVSEL# response.\nThe additional time is available only for interpreting the address and command after it is captured.\nOn the fifth cycle of the address phase (or earlier if all other devices have medium DEVSEL or faster), a catch-all \"subtractive decoding\" is allowed for some address ranges.\nThis is commonly used by an [ISA bus](https://bliptext.com/articles/isa-bus) bridge for addresses within its range (24 bits for memory and 16 bits for I/O).\nOn the sixth cycle, if there has been no response, the initiator may abort the transaction by deasserting FRAME#.\nThis is known as master abort termination and it is customary for PCI bus bridges to return all-ones data (0xFFFFFFFF) in this case.\nPCI devices, therefore, are generally designed to avoid using the all-ones value in important status registers, so that such an error can be easily detected by software.\n\n### Address phase timing\nNotes:\nOn the rising edge of clock 0, the initiator observes FRAME# and IRDY# both high, and GNT# low, so it drives the address, command, and asserts FRAME# in time for the rising edge of clock 1.\nTargets latch the address and begin decoding it.\nThey may respond with DEVSEL# in time for clock 2 (fast DEVSEL), 3 (medium) or 4 (slow).\nSubtractive decode devices, seeing no other response by clock 4, may respond on clock 5.\nIf the master does not see a response by clock 5, it will terminate the transaction and remove FRAME# on clock 6.\nTRDY# and STOP# are deasserted (high) during the address phase.\nThe initiator may assert IRDY# as soon as it is ready to transfer data, which could theoretically be as soon as clock 2.\n# [Peripheral Component Interconnect | upload.wikimedia.org/wikipedia/commons/e/e5/AddressPhaseTiming///wavedrom.svg]\n\n### Dual-cycle address\nTo allow 64-bit addressing, a master will present the address over two consecutive cycles.\nFirst, it sends the low-order address bits with a special \"dual-cycle address\" command on the C/BE[3:0]#.\nOn the following cycle, it sends the high-order address bits and the actual command.\nDual-address cycles are forbidden if the high-order address bits are zero, so devices that do not support 64-bit addressing can simply not respond to dual-cycle commands.\n

\n_ 0_  1_  2_  3_  4_  5_  6_        CLK _/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/\n___      GNT#    \\___/XXXXXXXXXXXXXXXXXXXXXXX\n_______    FRAME#        \\_______________________\n___ ___  AD[31:0] ---<___X___>--- (Low, then high bits)\n___ ___ _______________ C/BE[3:0]# ---<___X___X_______________ (DAC, then actual command)\n___________________________   DEVSEL#                \\___\\___\\___\\___\nFast Med Slow\n_  _   _   _   _   _   _   _        CLK _/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/\n0  1   2   3   4   5   6\n\n### Configuration access\nAddresses for PCI configuration space access use special decoding.\nFor these, the low-order address lines specify the offset of the desired PCI configuration register, and the high-order address lines are ignored.\nInstead, an additional address signal, the IDSEL input, must be high before a device may assert DEVSEL#.\nEach slot connects a different high-order address line to the IDSEL pin and is selected using [one-hot](https://bliptext.com/articles/one-hot) encoding on the upper address lines.\n\n## Data phases\nAfter the address phase (specifically, beginning with the cycle that DEVSEL# goes low) comes a burst of one or more data phases.\nIn all cases, the initiator drives active-low byte select signals on the C/BE[3:0]# lines, but the data on the AD[31:0] may be driven by the initiator (in case of writes) or target (in case of reads).\nDuring data phases, the C/BE[3:0]# lines are interpreted as active-low byte enables.\nIn case of a write, the asserted signals indicate which of the four bytes on the AD bus are to be written to the addressed location.\nIn the case of a read, they indicate which bytes the initiator is interested in.\nFor reads, it is always legal to ignore the byte-enable signals and simply return all 32 bits; cacheable memory resources are required to always return 32 valid bits.\nThe byte enables are mainly useful for I/O space accesses where reads have side effects.\nA data phase with all four C/BE# lines deasserted is explicitly permitted by the PCI standard, and must have no effect on the target other than to advance the address in the burst access in progress.\nThe data phase continues until both parties are ready to complete the transfer and continue to the next data phase.\nThe initiator asserts IRDY# (initiator ready) when it no longer needs to wait, while the target asserts TRDY# (target ready).\nWhichever side is providing the data must drive it on the AD bus before asserting its ready signal.\nOnce one of the participants asserts its ready signal, it may not become un-ready or otherwise alter its control signals until the end of the data phase.\nThe data recipient must latch the AD bus each cycle until it sees both IRDY# and TRDY# asserted, which marks the end of the current data phase and indicates that the just-latched data is the word to be transferred.\nTo maintain full burst speed, the data sender then has half a clock cycle after seeing both IRDY# and TRDY# asserted to drive the next word onto the AD bus.\n\n0_ 1_  2_  3_  4_  5_  6_  7_  8_  9_        CLK _/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/\n___        _______     ___ ___ ___   AD[31:0] ---<___XXXXXXXXX_______XXXXX___X___X___ (If a write)\n___            ___ _______ ___ ___   AD[31:0] ---<___>\n0_ 1_  2_  3_  4_  5_  6_  7_        CLK _/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\\n___ ___ ___ ___ ___  AD[31:0] ---<___X___X___X___X___>---<___>\n___ ___ ___ ___ ___ C/BE[3:0]# ---<___X___X___X___X___>---<___>\n|  |   |   |  ___      IRDY# ^^^^^^^^\\______________/   ^^^^^\n|  |   |   |  ___      TRDY# ^^^^^^^^\\______________/   ^^^^^\n|  |   |   |  ___    DEVSEL# ^^^^^^^^\\______________/   ^^^^^\n___     |   |   |  ___     FRAME#    \\_______________/ | ^^^^\\____\n_  _  |_  |_  |_  |_   _   _        CLK _/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\\n0  1   2   3   4   5   6   7\nOn clock edge 1, the initiator starts a transaction by driving an address, command, and asserting FRAME# The other signals are idle (indicated by ^^^), pulled high by the motherboard's pull-up resistors.\nThat might be their turnaround cycle.\nOn cycle 2, the target asserts both DEVSEL# and TRDY#.\nAs the initiator is also ready, a data transfer occurs.\nThis repeats for three more cycles, but before the last one (clock edge 5), the master deasserts FRAME#, indicating that this is the end.\nOn clock edge 6, the AD bus and FRAME# are undriven (turnaround cycle) and the other control lines are driven high for 1 cycle.\nOn clock edge 7, another initiator can start a different transaction.\nThis is also the turnaround cycle for the other control lines.\nThe equivalent read burst takes one more cycle, because the target must wait 1 cycle for the AD bus to turn around before it may assert TRDY#:\n\n0_ 1_  2_  3_  4_  5_  6_  7_  8_        CLK _/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\\n___    ___ ___ ___ ___   AD[31:0] ---<___>---<___X___X___X___>---<___>\n___ _______ ___ ___ ___ C/BE[3:0]# ---<___X_______X___X___X___>---<___>\n___         |   |   |   |  ___      IRDY#    ^^^^\\___________________/   ^^^^^\n___   _____ |   |   |   |  ___      TRDY#    ^^^^     \\______________/   ^^^^^\n___         |   |   |   |  ___    DEVSEL#    ^^^^\\___________________/   ^^^^^\n___         |   |   |  ___     FRAME#    \\___________________/ | ^^^^\\____\n_  _   _  |_  |_  |_  |_   _   _        CLK _/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\\n0  1   2   3   4   5   6   7   8\nA high-speed burst terminated by the target will have an extra cycle at the end:\n\n0_ 1_  2_  3_  4_  5_  6_  7_  8_        CLK _/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\\n___    ___ ___ ___ ___   AD[31:0] ---<___>---<___X___X___X___XXXX>\n___ _______ ___ ___ ___ ___ C/BE[3:0]# ---<___X_______X___X___X___X___>\n|  |   |   |      ___      IRDY# ^^^^^^^\\_______________________/\n_____ |  |   |   |  _______      TRDY# ^^^^^^^     \\______________/\n________________ |      ___      STOP# ^^^^^^^      |   |   | \\_______/\n|  |   |   |      ___    DEVSEL# ^^^^^^^\\_______________________/\n___         |   |   |   |  ___     FRAME#    \\_______________________/   ^^^^\n_  _   _  |_  |_  |_  |_   _   _        CLK _/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\\n0  1   2   3   4   5   6   7   8\nOn clock edge 6, the target indicates that it wants to stop (with data), but the initiator is already holding IRDY# low, so there is a fifth data phase (clock edge 7), during which no data is transferred.\n\n## Parity\nThe PCI bus detects parity errors, but does not attempt to correct them by retrying operations; it is purely a failure indication.\nDue to this, there is no need to detect the parity error before it has happened, and the PCI bus actually detects it a few cycles later.\nDuring a data phase, whichever device is driving the AD[31:0] lines computes even parity over them and the C/BE[3:0]# lines, and sends that out the PAR line one cycle later.\nAll access rules and turnaround cycles for the AD bus apply to the PAR line, just one cycle later.\nThe device listening on the AD bus checks the received parity and asserts the PERR# (parity error) line one cycle after that.\nThis generally generates a processor interrupt, and the processor can search the PCI bus for the device which detected the error.\nThe PERR# line is only used during data phases, once a target has been selected.\nIf a parity error is detected during an address phase (or the data phase of a Special Cycle), the devices which observe it assert the SERR# (System error) line.\nEven when some bytes are masked by the C/BE# lines and not in use, they must still have some defined value, and this value must be used to compute the parity.\n\n## Fast back-to-back transactions\nDue to the need for a turnaround cycle between different devices driving PCI bus signals, in general it is necessary to have an idle cycle between PCI bus transactions.\nHowever, in some circumstances it is permitted to skip this idle cycle, going directly from the final cycle of one transfer (IRDY# asserted, FRAME# deasserted) to the first cycle of the next (FRAME# asserted, IRDY# deasserted).\nAn initiator may only perform back-to-back transactions when:\nAdditional timing constraints may come from the need to turn around are the target control lines, particularly DEVSEL#.\nThe target deasserts DEVSEL#, driving it high, in the cycle following the final data phase, which in the case of back-to-back transactions is the first cycle of the address phase.\nThe second cycle of the address phase is then reserved for DEVSEL# turnaround, so if the target is different from the prior one, it must not assert DEVSEL# until the third cycle (medium DEVSEL speed).\nOne case where this problem cannot arise is if the initiator knows somehow (presumably because the addresses share sufficient high-order bits) that the second transfer is addressed to the same target as the prior one.\nIn that case, it may perform back-to-back transactions.\nAll PCI targets must support this.\nIt is also possible for the target to keep track of the requirements.\nIf it never does fast DEVSEL, they are met trivially.\nIf it does, it must wait until medium DEVSEL time unless:\nTargets that have this ability indicate it by a special bit in a PCI configuration register, and if all targets on a bus have it, all initiators may use back-to-back transfers freely.\nA subtractive decoding bus bridge must know to expect this extra delay in the event of back-to-back cycles, to advertise back-to-back support.\n\n## 64-bit PCI\nStarting from revision 2.1, the PCI specification includes optional 64-bit support.\nThis is provided via an extended connector which provides the 64-bit bus extensions AD[63:32], C/BE[7:4]#, and PAR64, and a number of additional power and ground pins.\nThe 64-bit PCI connector can be distinguished from a 32-bit connector by the additional 64-bit segment.\nMemory transactions between 64-bit devices may use all 64 bits to double the data transfer rate.\nNon-memory transactions (including configuration and I/O space accesses) may not use the 64-bit extension.\nDuring a 64-bit burst, burst addressing works just as in a 32-bit transfer, but the address is incremented twice per data phase.\nThe starting address must be 64-bit aligned; i.e. AD2 must be 0.\nThe data corresponding to the intervening addresses (with AD2 = 1) is carried on the upper half of the AD bus.\nTo initiate a 64-bit transaction, the initiator drives the starting address on the AD bus and asserts REQ64# at the same time as FRAME#.\nIf the selected target can support a 64-bit transfer for this transaction, it replies by asserting ACK64# at the same time as DEVSEL#.\nA target may decide on a per-transaction basis whether to allow a 64-bit transfer.\nIf REQ64# is asserted during the address phase, the initiator also drives the high 32 bits of the address and a copy of the bus command on the high half of the bus.\nIf the address requires 64 bits, a dual address cycle is still required, but the high half of the bus carries the upper half of the address and the final command code during both address phase cycles; this allows a 64-bit target to see the entire address and begin responding earlier.\nIf the initiator sees DEVSEL# asserted without ACK64#, it performs 32-bit data phases.\nThe data which would have been transferred on the upper half of the bus during the first data phase is instead transferred during the second data phase.\nTypically, the initiator drives all 64 bits of data before seeing DEVSEL#.\nIf ACK64# is missing, it may cease driving the upper half of the data bus.\nThe REQ64# and ACK64# lines are held asserted for the entire transaction save the last data phase and deasserted at the same time as FRAME# and DEVSEL#, respectively.\nThe PAR64 line operates just like the PAR line, but provides even parity over AD[63:32] and C/BE[7:4]#.\nIt is only valid for address phases if REQ64# is asserted.\nPAR64 is only valid for data phases if both REQ64# and ACK64# are asserted.\n\n## Cache snooping (obsolete)\nPCI originally included optional support for [write-back](https://bliptext.com/articles/write-back) [cache coherence](https://bliptext.com/articles/cache-coherence).\nThis required support by cacheable memory targets, which would listen to two pins from the cache on the bus, SDONE (snoop done) and SBO# (snoop backoff).\nBecause this was rarely implemented in practice, it was deleted from revision 2.2 of the PCI specification, and the pins re-used for [SMBus](https://bliptext.com/articles/smbus) access in revision 2.3.\nThe cache would watch all memory accesses, without asserting DEVSEL#.\nIf it noticed an access that might be cached, it would drive SDONE low (snoop not done).\nA coherence-supporting target would avoid completing a data phase (asserting TRDY#) until it observed SDONE high.\nIn the case of a write to data that was clean in the cache, the cache would only have to invalidate its copy and would assert SDONE as soon as this was established.\nHowever, if the cache contained dirty data, the cache would have to write it back before the access could proceed.\nso it would assert SBO# when raising SDONE.\nThis would signal the active target to assert STOP# rather than TRDY#, causing the initiator to disconnect and retry the operation later.\nIn the meantime, the cache would arbitrate for the bus and write its data back to memory.\nTargets supporting cache coherency are also required to terminate bursts before they cross cache lines.\n\n# Development tools\nWhen developing and/or troubleshooting the PCI bus, examination of hardware signals can be very important.\n[Logic analyzers](https://bliptext.com/articles/logic-analyzers) and [bus analyzers](https://bliptext.com/articles/bus-analyzer) are tools that collect, analyze, and decode signals for users to view in useful ways.\n# [A PCI POST card that displays power-on self-test (POST) numbers during BIOS startup | upload.wikimedia.org/wikipedia/commons/f/f4/POST///card///98usd.jpg]","current_revision":null,"created_by":"kACnuQmH5k9Nr5VNVEpVeg7XpvUmMctD","created_at":"2025-01-25T17:22:55.074Z","updated_at":"2025-01-25T17:22:55.074Z","search_vector":"'compon':2 'interconnect':3 'peripher':1","search_content":" \n \n**Name:** PCI  \n**Fullname:** PCI Local Bus  \n**Invent -date:** June 22, 1992  \n**Invent -name:** [Intel](https://bliptext.com/articles/intel)  \n**Replaces:** [ISA](https://bliptext.com/articles/industry-standard-architecture), E[ISA](https://bliptext.com/articles/industry-standard-architecture), [MCA](https://bliptext.com/articles/micro-channel-architecture), [VLB](https://bliptext.com/articles/vesa-local-bus)  \n**Super -date:** 2004  \n**Super -name:** [AGP](https://bliptext.com/articles/accelerated-graphics-port) for graphics (1997), [PCI Express](https://bliptext.com/articles/pci-express)  \n**Width:** 32 or 64  \n**Pin Count:** 124 [32-bit](https://bliptext.com/articles/32-bit-computing)  \n**Speed:** [Half-duplex](https://bliptext.com/articles/half-duplex): · 133 [MB](https://bliptext.com/articles/megabyte)/s (32-bit at 33 MHz – the standard configuration) · 266 [MB](https://bliptext.com/articles/megabyte)/s (32-bit at 66 MHz) · 266 [MB](https://bliptext.com/articles/megabyte)/s (64-bit at 33 MHz) · 533 [MB](https://bliptext.com/articles/megabyte)/s (64-bit at 66 MHz)  \n**Hotplug:** Optional  \n \n\n# \n**Peripheral Component Interconnect** (**PCI**) is a [local](https://bliptext.com/articles/local-[bus](https://bliptext.com/articles/[computer](https://bliptext.com/articles/computer)-bus)) [computer](https://bliptext.com/articles/computer) [bus](https://bliptext.com/articles/[computer](https://bliptext.com/articles/computer)-bus) for attaching [hardware](https://bliptext.com/articles/[computer](https://bliptext.com/articles/computer)-hardware) devices in a [computer](https://bliptext.com/articles/computer) and is part of the **PCI** Local Bus standard.\nThe PCI bus supports the functions found on a [[processor](https://bliptext.com/articles/processor-computing) bus](https://bliptext.com/articles/system-bus) but in a standardized format that is independent of any given [processor](https://bliptext.com/articles/processor-computing)'s native bus.\nDevices connected to the PCI bus appear to a [bus master](https://bliptext.com/articles/bus-mastering) to be connected directly to its own bus and are assigned addresses in the processor's [address space](https://bliptext.com/articles/address-space).\nIt is a [parallel](https://bliptext.com/articles/parallel-communication) bus, [synchronous](https://bliptext.com/articles/synchronous-circuit) to a single [bus clock](https://bliptext.com/articles/clock-signal).\nAttached devices can take either the form of an [integrated circuit](https://bliptext.com/articles/integrated-circuit) fitted onto the [motherboard](https://bliptext.com/articles/motherboard) (called a planar device in the PCI specification) or an [expansion card](https://bliptext.com/articles/expansion-card) that fits into a slot.\nThe PCI Local Bus was first implemented in [IBM PC compatibles](https://bliptext.com/articles/ibm-pc-compatible), where it displaced the combination of several slow [Industry Standard Architecture](https://bliptext.com/articles/industry-standard-architecture) (ISA) slots and one fast [VESA Local Bus](https://bliptext.com/articles/vesa-local-bus) (VLB) slot as the bus configuration.\nIt has subsequently been adopted for other computer types.\nTypical PCI cards used in PCs include: [network cards](https://bliptext.com/articles/network-card), [sound cards](https://bliptext.com/articles/sound-card), [modems](https://bliptext.com/articles/modem), extra ports such as Universal Serial Bus ([USB](https://bliptext.com/articles/usb)) or [serial](https://bliptext.com/articles/serial-port), [TV tuner cards](https://bliptext.com/articles/tv-tuner-card) and [hard disk drive](https://bliptext.com/articles/hard-disk-drive) [host adapters](https://bliptext.com/articles/host-adapter).\nPCI [video cards](https://bliptext.com/articles/video-card) replaced ISA and VLB cards until rising [bandwidth](https://bliptext.com/articles/bandwidth-computing) needs outgrew the abilities of PCI.\nThe preferred interface for video cards then became [Accelerated Graphics Port](https://bliptext.com/articles/accelerated-graphics-port) (AGP), a superset of PCI, before giving way to PCI Express.\nThe first version of PCI found in retail desktop computers was a [32-bit](https://bliptext.com/articles/32-bit-computing) bus using a 33 MHz bus clock and 5 V signaling, although the PCI 1.0 standard provided for a [64-bit](https://bliptext.com/articles/64-bit-computing) variant as well.\nThese have one locating notch in the card.\nVersion 2.0 of the PCI standard introduced 3.3 V slots, physically distinguished by a flipped physical connector to prevent accidental insertion of 5 V cards.\nUniversal cards, which can operate on either voltage, have two notches.\nVersion 2.1 of the PCI standard introduced optional 66 MHz operation.\nA server-oriented variant of PCI, PCI Extended ([PCI-X](https://bliptext.com/articles/pci-x)) operated at frequencies up to 133 MHz for [PCI-X](https://bliptext.com/articles/pci-x) 1.0 and up to 533 MHz for [PCI-X](https://bliptext.com/articles/pci-x) 2.0.\nAn internal connector for laptop cards, called **Mini PCI**, was introduced in version 2.2 of the PCI specification.\nThe PCI bus was also adopted for an external laptop connector standard – the [CardBus](https://bliptext.com/articles/cardbus).\nThe first PCI specification was developed by [Intel](https://bliptext.com/articles/intel), but subsequent development of the standard became the responsibility of the PCI Special Interest Group ([PCI-SIG](https://bliptext.com/articles/pci-sig)).\nPCI and PCI-X sometimes are referred to as either Parallel PCI or Conventional PCI to distinguish them technologically from their more recent successor [PCI Express](https://bliptext.com/articles/pci-express), which adopted a [serial](https://bliptext.com/articles/serial-communication), lane-based architecture.\nPCI's heyday in the desktop computer market was approximately 1995 to 2005.\nPCI and PCI-X have become obsolete for most purposes and has largely disappeared from many other modern motherboards since 2013; however they are still common on some modern desktops for the purposes of [backward compatibility](https://bliptext.com/articles/backward-compatibility) and the relative low cost to produce.\nAnother common modern application of parallel PCI is in [industrial PCs](https://bliptext.com/articles/industrial-pc), where many specialized expansion cards, used here, never transitioned to PCI Express, just as with some ISA cards.\nMany kinds of devices formerly available on PCI expansion cards are now commonly integrated onto motherboards or available in USB and PCI Express versions.\n\n# History\nWork on PCI began at the [Intel Architecture Labs](https://bliptext.com/articles/intel-architecture-labs) (IAL, also Architecture Development Lab) c. 1990.\nA team of primarily IAL engineers defined the architecture and developed a proof of concept chipset and platform (Saturn) partnering with teams in the company's desktop PC systems and core logic product organizations.\nPCI was immediately put to use in servers, replacing [Micro Channel architecture](https://bliptext.com/articles/micro-channel-architecture) (MCA) and [Extended Industry Standard Architecture](https://bliptext.com/articles/extended-industry-standard-architecture) (EISA) as the server expansion bus of choice.\nIn mainstream PCs, PCI was slower to replace [VLB](https://bliptext.com/articles/vesa-local-bus), and did not gain significant market penetration until late 1994 in second-generation [Pentium](https://bliptext.com/articles/p5-microarchitecture) PCs.\nBy 1996, VLB was all but extinct, and manufacturers had adopted PCI even for [Intel 80486](https://bliptext.com/articles/intel-80486) (486) computers.\nEISA continued to be used alongside PCI through 2000.\n[Apple Computer](https://bliptext.com/articles/apple-computer) adopted PCI for professional [Power Macintosh](https://bliptext.com/articles/power-macintosh) computers (replacing [NuBus](https://bliptext.com/articles/nubus)) in mid-1995, and the consumer [Performa](https://bliptext.com/articles/macintosh-performa) product line (replacing LC [Processor Direct Slot](https://bliptext.com/articles/processor-direct-slot) (PDS)) in mid-1996.\nOutside the server market, the 64-bit version of plain PCI remained rare in practice though, although it was used for example by all [(post-iMac) G3](https://bliptext.com/articles/power-macintosh-g3) and [G4 Power Macintosh computers](https://bliptext.com/articles/power-mac-g4).\nLater revisions of PCI added new features and performance improvements, including a 66 [MHz](https://bliptext.com/articles/megahertz) 3.3 [V](https://bliptext.com/articles/volt) standard and 133 [MHz](https://bliptext.com/articles/megahertz) [PCI-X](https://bliptext.com/articles/pci-x), and the adaptation of PCI signaling to other form factors.\nBoth PCI-X 1.0b and PCI-X 2.0 are backward compatible with some PCI standards.\nThese revisions were used on server hardware but consumer PC hardware remained nearly all 32-bit, 33 MHz and 5 volt.\nThe PCI-SIG introduced the serial [PCI Express](https://bliptext.com/articles/pci-express) in c. 2004.\nSince then, motherboard manufacturers have included progressively fewer PCI slots in favor of the new standard.\nMany new motherboards do not provide PCI slots at all, as of late 2013.\n# [A typical 32-bit, 5 V-only PCI card, in this case, a SCSI adapter from Adaptec | upload.wikimedia.org/wikipedia/commons/d/d2/Adaptec///AHA-2940AU.png]\n# [A motherboard with two 32-bit PCI slots and two sizes of PCI Express slots | upload.wikimedia.org/wikipedia/commons/0/0c/PCI///und///PCIe///Slots.jpg]\n\n# Auto configuration\nPCI provides separate memory and [memory-mapped I/O](https://bliptext.com/articles/memory-mapped-i-o) port address spaces for the [x86](https://bliptext.com/articles/x86) processor family, [64](https://bliptext.com/articles/64-bit-computing) and [32 bits](https://bliptext.com/articles/32-bit-computing), respectively.\nAddresses in these [address spaces](https://bliptext.com/articles/address-space) are assigned by software.\nA third address space, called the [PCI Configuration Space](https://bliptext.com/articles/pci-configuration-space), which uses a fixed addressing scheme, allows software to determine the amount of memory and I/O address space needed by each device.\nEach device can request up to six areas of memory space or [input/output](https://bliptext.com/articles/input-output) (I/O) port space via its configuration space registers.\nIn a typical system, the [firmware](https://bliptext.com/articles/firmware) (or [operating system](https://bliptext.com/articles/operating-system)) queries all PCI buses at startup time (via [PCI Configuration Space](https://bliptext.com/articles/pci-configuration-space)) to find out what devices are present and what system resources (memory space, I/O space, interrupt lines, etc.) each needs.\nIt then allocates the resources and tells each device what its allocation is.\nThe PCI configuration space also contains a small amount of device type information, which helps an operating system choose device drivers for it, or at least to have a dialogue with a user about the system configuration.\nDevices may have an on-board [read-only memory](https://bliptext.com/articles/read-only-memory) (ROM) containing executable code for x86 or [PA-RISC](https://bliptext.com/articles/pa-risc) processors, an [Open Firmware](https://bliptext.com/articles/open-firmware) driver, or an [Option ROM](https://bliptext.com/articles/option-rom).\nThese are typically needed for devices used during system startup, before device drivers are loaded by the operating system.\nIn addition, there are PCI Latency Timers that are a mechanism for PCI Bus-Mastering devices to share the PCI bus fairly.\n\"Fair\" in this case means that devices will not use such a large portion of the available PCI bus bandwidth that other devices are not able to get needed work done.\nNote, this does not apply to PCI Express.\n\"How this works is that each PCI device that can operate in bus-master mode is required to implement a timer, called the Latency Timer, that limits the time that device can hold the PCI bus. The timer starts when the device gains bus ownership, and counts down at the rate of the PCI clock. When the counter reaches zero, the device is required to release the bus. If no other devices are waiting for bus ownership, it may simply grab the bus again and transfer more data.\"\n\n# Interrupts\nDevices are required to follow a protocol so that the [interrupt-request](https://bliptext.com/articles/interrupt-request) (IRQ) lines can be shared.\nThe PCI bus includes four interrupt lines, INTA# through INTD#, all of which are available to each device.\nUp to eight PCI devices share the same IRQ line (INTINA# through INTINH#) in [APIC](https://bliptext.com/articles/advanced-programmable-interrupt-controller)-enabled x86 systems.\nInterrupt lines are not wired in parallel as are the other PCI bus lines.\nThe positions of the interrupt lines rotate between slots, so what appears to one device as the INTA# line is INTB# to the next and INTC# to the one after that.\nSingle-function devices usually use their INTA# for interrupt signaling, so the device load is spread fairly evenly across the four available interrupt lines.\nThis alleviates a common problem with sharing interrupts.\nThe mapping of PCI interrupt lines onto system interrupt lines, through the PCI host bridge, is implementation-dependent.\nPlatform-specific [firmware](https://bliptext.com/articles/firmware) or operating system code is meant to know this, and set the \"interrupt line\" field in each device's configuration space indicating which IRQ it is connected to.\nPCI interrupt lines are [level-triggered](https://bliptext.com/articles/interrupt).\nThis was chosen over [edge-triggering](https://bliptext.com/articles/interrupt) to gain an advantage when servicing a shared interrupt line, and for robustness: edge-triggered interrupts are easy to miss.\nLater revisions of the PCI specification add support for [message-signaled interrupts](https://bliptext.com/articles/message-signaled-interrupts).\nIn this system, a device signals its need for service by performing a memory write, rather than by asserting a dedicated line.\nThis alleviates the problem of scarcity of interrupt lines.\nEven if interrupt vectors are still shared, it does not suffer the sharing problems of level-triggered interrupts.\nIt also resolves the routing problem, because the memory write is not unpredictably modified between device and host.\nFinally, because the message [signaling is in-band](https://bliptext.com/articles/in-band-signaling), it resolves some synchronization problems that can occur with posted writes and [out-of-band](https://bliptext.com/articles/out-of-band-data) interrupt lines.\n[PCI Express](https://bliptext.com/articles/pci-express) does not have physical interrupt lines at all.\nIt uses message-signaled interrupts exclusively.\n\n# Conventional hardware specifications\nThese specifications represent the most common version of PCI used in normal PCs:\nThe PCI specification also provides options for 3.3 V signaling, [64-bit](https://bliptext.com/articles/64-bit-computing) bus width, and 66 MHz clocking, but these are not commonly encountered outside of PCI-X support on server motherboards.\nThe PCI bus arbiter performs bus arbitration among multiple masters on the PCI bus.\nAny number of bus masters can reside on the PCI bus, as well as requests for the bus.\nOne pair of request and grant signals is dedicated to each bus master.\n# [Diagram showing the different key positions for 32-bit and 64-bit PCI cards | upload.wikimedia.org/wikipedia/commons/1/15/PCI///Keying.svg]\n\n## Card voltage and keying\nTypical PCI cards have either one or two key notches, depending on their signaling voltage.\nCards requiring 3.3 volts have a notch 56.21 mm from the card backplate; those requiring 5 volts have a notch 104.41 mm from the backplate.\nThis allows cards to be fitted only into slots with a voltage they support.\n\"Universal cards\" accepting either voltage have both key notches.\n# [A PCI-X Gigabit Ethernet expansion card with both 5 V and 3.3 V support notches, side B toward the camera | upload.wikimedia.org/wikipedia/commons/c/c5/Intelpromtserverpcixadapter1000mta342.jpg]\n\n## Connector pinout\nThe PCI connector is defined as having 62 contacts on each side of the [edge connector](https://bliptext.com/articles/edge-connector), but two or four of them are replaced by key notches, so a card has 60 or 58 contacts on each side.\nSide A refers to the 'solder side' and side B refers to the 'component side': if the card is held with the connector pointing down, a view of side A will have the backplate on the right, whereas a view of side B will have the backplate on the left.\nThe pinout of B and A sides are as follows, looking down into the motherboard connector (pins A1 and B1 are closest to backplate).\n64-bit PCI extends this by an additional 32 contacts on each side which provide AD[63:32], C/BE[7:4]#, the PAR64 parity signal, and a number of power and ground pins.\nMost lines are connected to each slot in parallel.\nThe exceptions are:\nNotes:\n\n## Mixing of 32-bit and 64-bit PCI cards in different width slots\nMost 32-bit PCI cards will function properly in 64-bit PCI-X slots, but the bus clock rate will be limited to the clock frequency of the slowest card, an inherent limitation of PCI's shared bus topology.\nFor example, when a PCI 2.3, 66-MHz peripheral is installed into a PCI-X bus capable of 133 MHz, the entire bus backplane will be limited to 66 MHz.\nTo get around this limitation, many motherboards have two or more PCI/PCI-X buses, with one bus intended for use with high-speed PCI-X peripherals, and the other bus intended for general-purpose peripherals.\nMany 64-bit PCI-X cards are designed to work in 32-bit mode if inserted in shorter 32-bit connectors, with some loss of performance.\nAn example of this is the Adaptec 29160 64-bit [SCSI](https://bliptext.com/articles/scsi) interface card.\nHowever, some 64-bit PCI-X cards do not work in standard 32-bit PCI slots.\nInstalling a 64-bit PCI-X card in a 32-bit slot will leave the 64-bit portion of the card edge connector not connected and overhanging.\nThis requires that there be no motherboard components positioned so as to mechanically obstruct the overhanging portion of the card edge connector.\n# [A semi-inserted PCI-X card in a 32-bit PCI slot, illustrating the need for the rightmost notch and the extra room on the motherboard to remain backward compatible | upload.wikimedia.org/wikipedia/commons/6/64/PCI-X///in///a///32-bit///slot.jpg]\n# [64-bit SCSI card working in a 32-bit PCI slot | upload.wikimedia.org/wikipedia/commons/e/ed/64bit///PCI///SCSI///card///in///a///32bit///PCI///slot.jpg]\n\n# Physical dimensions\nPCI brackets heights:\nPCI Card lengths (Standard Bracket & 3.3 V):\nPCI Card lengths (Low Profile Bracket & 3.3 V):\n\n## Mini PCI\n**Mini PCI** was added to PCI version 2.2 for use in [laptops](https://bliptext.com/articles/laptop) and some routers; it uses a 32-bit, 33 MHz bus with powered connections (3.3 V only; 5 V is limited to 100 mA) and support for [bus mastering](https://bliptext.com/articles/bus-mastering) and [DMA](https://bliptext.com/articles/direct-memory-access).\nThe standard size for Mini PCI cards is approximately a quarter of their full-sized counterparts.\nThere is no access to the card from outside the case, unlike desktop PCI cards with brackets carrying connectors.\nThis limits the kinds of functions a Mini PCI card can perform.\nMany Mini PCI devices were developed such as [Wi-Fi](https://bliptext.com/articles/wi-fi), [Fast Ethernet](https://bliptext.com/articles/fast-ethernet), [Bluetooth](https://bliptext.com/articles/bluetooth), [modems](https://bliptext.com/articles/modem) (often Win[modems](https://bliptext.com/articles/modem)), [sound cards](https://bliptext.com/articles/sound-card), [cryptographic accelerators](https://bliptext.com/articles/cryptographic-accelerator), [SCSI](https://bliptext.com/articles/scsi), [IDE](https://bliptext.com/articles/integrated-drive-electronics)–[ATA](https://bliptext.com/articles/at-attachment), S[ATA](https://bliptext.com/articles/at-attachment) controllers and combination cards.\nMini PCI cards can be used with regular PCI-equipped hardware, using Mini PCI-to-PCI converters.\nMini PCI has been superseded by the much narrower [PCI Express Mini Card](https://bliptext.com/articles/pci-express-mini-card)\n# [A Mini PCI slot | upload.wikimedia.org/wikipedia/commons/c/c6/Mini///PCI///slot///PNr%C2%B00344.jpg]\n# [Mini PCI Wi-Fi card Type IIIB | upload.wikimedia.org/wikipedia/commons/b/b8/MiniPCI///WiFi.jpg]\n# [PCI-to-MiniPCI converter Type III | upload.wikimedia.org/wikipedia/commons/b/b1/MiniPCI///PCI.jpg]\n# [MiniPCI and MiniPCI Express cards in comparison | upload.wikimedia.org/wikipedia/commons/d/d8/MiniPCI///and///MiniPCI///Express///cards.jpg]\n\n### Technical details of Mini PCI\nMini PCI cards have a 2 W maximum power consumption, which limits the functionality that can be implemented in this form factor.\nThey also are required to support the CLKRUN# PCI signal used to start and stop the PCI clock for power management purposes.\nThere are three card [form factors](https://bliptext.com/articles/computer-form-factor): Type I, Type II, and Type III cards.\nThe card connector used for each type include: Type I and II use a 100-pin stacking connector, while Type III uses a 124-pin edge connector, i.e. the connector for Types I and II differs from that for Type III, where the connector is on the edge of a card, like with a [SO-DIMM](https://bliptext.com/articles/so-dimm).\nThe additional 24 pins provide the extra signals required to route [I/O](https://bliptext.com/articles/input-output) back through the system connector (audio, [AC-Link](https://bliptext.com/articles/ac-97), [LAN](https://bliptext.com/articles/lan), phone-line interface).\nType II cards have RJ11 and RJ45 mounted connectors.\nThese cards must be located at the edge of the computer or docking station so that the RJ11 and RJ45 ports can be mounted for external access.\nMini PCI is distinct from 144-pin Micro PCI.\n\n# PCI bus transactions\nPCI bus traffic consists of a series of PCI bus transactions.\nEach transaction consists of an address phase followed by one or more data phases.\nThe direction of the data phases may be from initiator to target (write transaction) or vice versa (read transaction), but all of the data phases must be in the same direction.\nEither party may pause or halt the data phases at any point.\n(One common example is a low-performance PCI device that does not support [burst transactions](https://bliptext.com/articles/burst-mode-computing), and always halts a transaction after the first data phase.)\nAny PCI device may initiate a transaction.\nFirst, it must request permission from a PCI bus arbiter on the motherboard.\nThe arbiter grants permission to one of the requesting devices.\nThe initiator begins the address phase by broadcasting a 32-bit address plus a [4-bit](https://bliptext.com/articles/4-bit-computing) command code, then waits for a target to respond.\nAll other devices examine this address and one of them responds a few cycles later.\n64-bit addressing is done using a two-stage address phase.\nThe initiator broadcasts the low 32 address bits, accompanied by a special \"dual address cycle\" command code.\nDevices that do not support 64-bit addressing can simply not respond to that command code.\nThe next cycle, the initiator transmits the high 32 address bits, plus the real command code.\nThe transaction operates identically from that point on.\nTo ensure compatibility with 32-bit PCI devices, it is forbidden to use a dual address cycle if not necessary, i.e. if the high-order address bits are all zero.\nWhile the PCI bus transfers 32 bits per data phase, the initiator transmits 4 active-low byte enable signals indicating which [8-bit](https://bliptext.com/articles/8-bit-computing) bytes are to be considered significant.\nIn particular, a write must affect only the enabled bytes in the target PCI device.\nThey are of little importance for memory reads, but I/O reads might have side effects.\nThe PCI standard explicitly allows a data phase with no bytes enabled, which must behave as a no-op.\n\n## PCI address spaces\nPCI has three address spaces: memory, I/O address, and configuration.\nMemory addresses are 32 bits (optionally 64 bits) in size, support [caching](https://bliptext.com/articles/cache-computing) and can be burst transactions.\nI/O addresses are for compatibility with the Intel [x86 architecture](https://bliptext.com/articles/x86-architecture)'s I/O port address space.\nAlthough the PCI bus specification allows burst transactions in any address space, most devices only support it for memory addresses and not I/O.\nFinally, [PCI configuration space](https://bliptext.com/articles/pci-configuration-space) provides access to 256 bytes of special configuration registers per PCI device.\nEach PCI slot gets its own configuration space address range.\nThe registers are used to configure devices memory and I/O address ranges they should respond to from transaction initiators.\nWhen a computer is first turned on, all PCI devices respond only to their configuration space accesses.\nThe computer's BIOS scans for devices and assigns Memory and I/O address ranges to them.\nIf an address is not claimed by any device, the transaction initiator's address phase will time out causing the initiator to abort the operation.\nIn case of reads, it is customary to supply all-ones for the read data value (0xFFFFFFFF) in this case.\nPCI devices therefore generally attempt to avoid using the all-ones value in important status registers, so that such an error can be easily detected by software.\n\n## PCI command codes\nThere are 16 possible 4-bit command codes, and 12 of them are assigned.\nWith the exception of the unique dual address cycle, the least significant bit of the command code indicates whether the following data phases are a read (data sent from target to initiator) or a write (data sent from an initiator to target).\nPCI targets must examine the command code as well as the address and not respond to address phases that specify an unsupported command code.\nThe commands that refer to cache lines depend on the [PCI configuration space](https://bliptext.com/articles/pci-configuration-space) cache line size register being set up properly; they may not be used until that has been done.\n\n# PCI bus latency\nSoon after promulgation of the PCI specification, it was discovered that lengthy transactions by some devices, due to slow acknowledgments, long data bursts, or some combination, could cause [buffer underrun](https://bliptext.com/articles/buffer-underrun) or overrun in other devices.\nRecommendations on the timing of individual phases in Revision 2.0 were made mandatory in revision 2.1:\nAdditionally, as of revision 2.1, all initiators capable of bursting more than two data phases must implement a programmable latency timer.\nThe timer starts counting clock cycles when a transaction starts (initiator asserts FRAME#).\nIf the timer has expired and the arbiter has removed GNT#, then the initiator must terminate the transaction at the next legal opportunity.\nThis is usually the next data phase, but Memory Write and Invalidate transactions must continue to the end of the cache line.\n\n## Delayed transactions\nDevices unable to meet those timing restrictions must use a combination of [posted writes](https://bliptext.com/articles/) (for memory writes) and delayed transactions (for other writes and all reads).\nIn a delayed transaction, the target records the transaction (including the write data) internally and aborts (asserts STOP# rather than TRDY#) the first data phase.\nThe initiator must retry exactly the same transaction later.\nIn the interim, the target internally performs the transaction, and waits for the retried transaction.\nWhen the retried transaction is seen, the buffered result is delivered.\nA device may be the target of other transactions while completing one delayed transaction; it must remember the transaction type, address, byte selects and (if a write) data value, and only complete the correct transaction.\nIf the target has a limit on the number of delayed transactions that it can record internally (simple targets may impose a limit of 1), it will force those transactions to retry without recording them.\nThey will be dealt with when the current delayed transaction is completed.\nIf two initiators attempt the same transaction, a delayed transaction begun by one may have its result delivered to the other; this is harmless.\nA target abandons a delayed transaction when a retry succeeds in delivering the buffered result, the bus is reset, or when 215=32768 clock cycles (approximately 1 ms) elapse without seeing a retry.\nThe latter should never happen in normal operation, but it prevents a [deadlock](https://bliptext.com/articles/deadlock-computer-science) of the whole bus if one initiator is reset or malfunctions.\n\n# PCI bus bridges\nThe PCI standard permits multiple independent PCI buses to be connected by bus bridges that will forward operations on one bus to another when required.\nAlthough PCI tends not to use many bus bridges, [PCI Express](https://bliptext.com/articles/pci-express) systems use many PCI-to-PCI bridge usually called [PCI Express](https://bliptext.com/articles/pci-express) Root Port; each [PCI Express](https://bliptext.com/articles/pci-express) slot appears to be a separate bus, connected by a bridge to the others.\nThe PCI host bridge (usually [northbridge](https://bliptext.com/articles/northbridge-computing) in x86 platforms) interconnect between CPU, main memory and PCI bus.\n\n## Posted writes\nGenerally, when a bus bridge sees a transaction on one bus that must be forwarded to the other, the original transaction must wait until the forwarded transaction completes before a result is ready.\nOne notable exception occurs in the case of memory writes.\nHere, the bridge may record the write data internally (if it has room) and signal completion of the write before the forwarded write has completed.\nOr, indeed, before it has begun.\nSuch \"sent but not yet arrived\" writes are referred to as \"posted writes\", by analogy with a postal mail message.\nAlthough they offer great opportunity for performance gains, the rules governing what is permissible are somewhat intricate.\n\n## Combining, merging, and collapsing\nThe PCI standard permits bus bridges to convert multiple bus transactions into one larger transaction under certain situations.\nThis can improve the efficiency of the PCI bus.\n\n### Combining\nWrite transactions to consecutive addresses may be combined into a longer burst write, as long as the order of the accesses in the burst is the same as the order of the original writes.\nIt is permissible to insert extra data phases with all byte enables turned off if the writes are almost consecutive.\n\n### Merging\nMultiple writes to disjoint portions of the same word may be merged into a single write with multiple byte enables asserted.\nIn this case, writes that were presented to the bus bridge in a particular order are merged so they occur at the same time when forwarded.\n\n### Collapsing\nMultiple writes to the same byte or bytes may not be combined, for example, by performing only the second write and skipping the first write that was overwritten.\nThis is because the PCI specification permits writes to have side effects.\n\n# PCI bus signals\nPCI bus transactions are controlled by five main control signals, two driven by the initiator of a transaction (FRAME# and IRDY#), and three driven by the target (DEVSEL#, TRDY#, and STOP#).\nThere are two additional arbitration signals (REQ# and GNT#) that are used to obtain permission to initiate a transaction.\nAll are [active-low](https://bliptext.com/articles/active-low), meaning that the active or asserted state is a low [voltage](https://bliptext.com/articles/voltage).\nPull-up resistors on the motherboard ensure they will remain high (inactive or deasserted) if not driven by any device, but the PCI bus does not depend on the resistors to change the signal level; all devices drive the signals high for one cycle before [ceasing to drive](https://bliptext.com/articles/three-state-logic) the signals.\n\n## Signal timing\nAll PCI bus signals are sampled on the rising edge of the clock.\nSignals nominally change on the falling edge of the clock, giving each PCI device approximately one half a clock cycle to decide how to respond to the signals it observed on the rising edge, and one half a clock cycle to transmit its response to the other device.\nThe PCI bus requires that every time the device driving a PCI bus signal changes, one turnaround cycle must elapse between the time the one device stops driving the signal and the other device starts.\nWithout this, there might be a period when both devices were driving the signal, which would interfere with bus operation.\nThe combination of this turnaround cycle and the requirement to drive a control line high for one cycle before ceasing to drive it means that each of the main control lines must be high for a minimum of two cycles when changing owners.\nThe PCI bus protocol is designed so this is rarely a limitation; only in a few special cases (notably [fast back-to-back transactions](https://bliptext.com/articles/)) is it necessary to insert additional delay to meet this requirement.\n\n## Arbitration\nAny device on a PCI bus that is capable of acting as a [bus master](https://bliptext.com/articles/bus-master) may initiate a transaction with any other device.\nTo ensure that only one transaction is initiated at a time, each master must first wait for a bus grant signal, GNT#, from an arbiter located on the motherboard.\nEach device has a separate request line REQ# that requests the bus, but the arbiter may \"park\" the bus grant signal at any device if there are no current requests.\nThe arbiter may remove GNT# at any time.\nA device that loses GNT# may complete its current transaction, but may not start one (by asserting FRAME#) unless it observes GNT# asserted the cycle before it begins.\nThe arbiter may also provide GNT# at any time, including during another master's transaction.\nDuring a transaction, either FRAME# or IRDY# or both are asserted; when both are deasserted, the bus is idle.\nA device may initiate a transaction at any time that GNT# is asserted and the bus is idle.\n\n## Address phase\nA PCI bus transaction begins with an address phase.\nThe initiator (usually a [chipset](https://bliptext.com/articles/chipset)), seeing that it has GNT# and the bus is idle, drives the target address onto the AD[31:0] lines, the associated command (e.g. memory read, or I/O write) on the C/BE[3:0]# lines, and pulls FRAME# low.\nEach other device examines the address and command and decides whether to respond as the target by asserting DEVSEL#.\nA device must respond by asserting DEVSEL# within 3 cycles.\nDevices that promise to respond within 1 or 2 cycles are said to have \"fast DEVSEL\" or \"medium DEVSEL\", respectively.\n(Actually, the time to respond is 2.5 cycles, since PCI devices must transmit all signals half a cycle early so that they can be received three cycles later.)\nA device must [latch](https://bliptext.com/articles/latch-electronics) the address on the first cycle; the initiator is required to remove the address and command from the bus on the following cycle, even before receiving a DEVSEL# response.\nThe additional time is available only for interpreting the address and command after it is captured.\nOn the fifth cycle of the address phase (or earlier if all other devices have medium DEVSEL or faster), a catch-all \"subtractive decoding\" is allowed for some address ranges.\nThis is commonly used by an [ISA bus](https://bliptext.com/articles/isa-bus) bridge for addresses within its range (24 bits for memory and 16 bits for I/O).\nOn the sixth cycle, if there has been no response, the initiator may abort the transaction by deasserting FRAME#.\nThis is known as master abort termination and it is customary for PCI bus bridges to return all-ones data (0xFFFFFFFF) in this case.\nPCI devices, therefore, are generally designed to avoid using the all-ones value in important status registers, so that such an error can be easily detected by software.\n\n### Address phase timing\nNotes:\nOn the rising edge of clock 0, the initiator observes FRAME# and IRDY# both high, and GNT# low, so it drives the address, command, and asserts FRAME# in time for the rising edge of clock 1.\nTargets latch the address and begin decoding it.\nThey may respond with DEVSEL# in time for clock 2 (fast DEVSEL), 3 (medium) or 4 (slow).\nSubtractive decode devices, seeing no other response by clock 4, may respond on clock 5.\nIf the master does not see a response by clock 5, it will terminate the transaction and remove FRAME# on clock 6.\nTRDY# and STOP# are deasserted (high) during the address phase.\nThe initiator may assert IRDY# as soon as it is ready to transfer data, which could theoretically be as soon as clock 2.\n# [Peripheral Component Interconnect | upload.wikimedia.org/wikipedia/commons/e/e5/AddressPhaseTiming///wavedrom.svg]\n\n### Dual-cycle address\nTo allow 64-bit addressing, a master will present the address over two consecutive cycles.\nFirst, it sends the low-order address bits with a special \"dual-cycle address\" command on the C/BE[3:0]#.\nOn the following cycle, it sends the high-order address bits and the actual command.\nDual-address cycles are forbidden if the high-order address bits are zero, so devices that do not support 64-bit addressing can simply not respond to dual-cycle commands.\n \n_ 0_  1_  2_  3_  4_  5_  6_        CLK _/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/\n___      GNT#    \\___/XXXXXXXXXXXXXXXXXXXXXXX\n_______    FRAME#        \\_______________________\n___ ___  AD[31:0] --- --- (Low, then high bits)\n___ ___ _______________ C/BE[3:0]# --- \n0_ 1_  2_  3_  4_  5_  6_  7_  8_  9_        CLK _/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/\n___        _______     ___ ___ ___   AD[31:0] ---  \n0_ 1_  2_  3_  4_  5_  6_  7_        CLK _/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\\n___ ___ ___ ___ ___  AD[31:0] --- --- \n___ ___ ___ ___ ___ C/BE[3:0]# --- --- \n|  |   |   |  ___      IRDY# ^^^^^^^^\\______________/   ^^^^^\n|  |   |   |  ___      TRDY# ^^^^^^^^\\______________/   ^^^^^\n|  |   |   |  ___    DEVSEL# ^^^^^^^^\\______________/   ^^^^^\n___     |   |   |  ___     FRAME#    \\_______________/ | ^^^^\\____\n_  _  |_  |_  |_  |_   _   _        CLK _/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\\n0  1   2   3   4   5   6   7\nOn clock edge 1, the initiator starts a transaction by driving an address, command, and asserting FRAME# The other signals are idle (indicated by ^^^), pulled high by the motherboard's pull-up resistors.\nThat might be their turnaround cycle.\nOn cycle 2, the target asserts both DEVSEL# and TRDY#.\nAs the initiator is also ready, a data transfer occurs.\nThis repeats for three more cycles, but before the last one (clock edge 5), the master deasserts FRAME#, indicating that this is the end.\nOn clock edge 6, the AD bus and FRAME# are undriven (turnaround cycle) and the other control lines are driven high for 1 cycle.\nOn clock edge 7, another initiator can start a different transaction.\nThis is also the turnaround cycle for the other control lines.\nThe equivalent read burst takes one more cycle, because the target must wait 1 cycle for the AD bus to turn around before it may assert TRDY#:\n \n0_ 1_  2_  3_  4_  5_  6_  7_  8_        CLK _/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\\n___    ___ ___ ___ ___   AD[31:0] --- --- --- \n___ _______ ___ ___ ___ C/BE[3:0]# --- --- \n___         |   |   |   |  ___      IRDY#    ^^^^\\___________________/   ^^^^^\n___   _____ |   |   |   |  ___      TRDY#    ^^^^     \\______________/   ^^^^^\n___         |   |   |   |  ___    DEVSEL#    ^^^^\\___________________/   ^^^^^\n___         |   |   |  ___     FRAME#    \\___________________/ | ^^^^\\____\n_  _   _  |_  |_  |_  |_   _   _        CLK _/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\\n0  1   2   3   4   5   6   7   8\nA high-speed burst terminated by the target will have an extra cycle at the end:\n \n0_ 1_  2_  3_  4_  5_  6_  7_  8_        CLK _/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\\n___    ___ ___ ___ ___   AD[31:0] --- --- \n___ _______ ___ ___ ___ ___ C/BE[3:0]# --- \n|  |   |   |      ___      IRDY# ^^^^^^^\\_______________________/\n_____ |  |   |   |  _______      TRDY# ^^^^^^^     \\______________/\n________________ |      ___      STOP# ^^^^^^^      |   |   | \\_______/\n|  |   |   |      ___    DEVSEL# ^^^^^^^\\_______________________/\n___         |   |   |   |  ___     FRAME#    \\_______________________/   ^^^^\n_  _   _  |_  |_  |_  |_   _   _        CLK _/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\_/ \\\n0  1   2   3   4   5   6   7   8\nOn clock edge 6, the target indicates that it wants to stop (with data), but the initiator is already holding IRDY# low, so there is a fifth data phase (clock edge 7), during which no data is transferred.\n\n## Parity\nThe PCI bus detects parity errors, but does not attempt to correct them by retrying operations; it is purely a failure indication.\nDue to this, there is no need to detect the parity error before it has happened, and the PCI bus actually detects it a few cycles later.\nDuring a data phase, whichever device is driving the AD[31:0] lines computes even parity over them and the C/BE[3:0]# lines, and sends that out the PAR line one cycle later.\nAll access rules and turnaround cycles for the AD bus apply to the PAR line, just one cycle later.\nThe device listening on the AD bus checks the received parity and asserts the PERR# (parity error) line one cycle after that.\nThis generally generates a processor interrupt, and the processor can search the PCI bus for the device which detected the error.\nThe PERR# line is only used during data phases, once a target has been selected.\nIf a parity error is detected during an address phase (or the data phase of a Special Cycle), the devices which observe it assert the SERR# (System error) line.\nEven when some bytes are masked by the C/BE# lines and not in use, they must still have some defined value, and this value must be used to compute the parity.\n\n## Fast back-to-back transactions\nDue to the need for a turnaround cycle between different devices driving PCI bus signals, in general it is necessary to have an idle cycle between PCI bus transactions.\nHowever, in some circumstances it is permitted to skip this idle cycle, going directly from the final cycle of one transfer (IRDY# asserted, FRAME# deasserted) to the first cycle of the next (FRAME# asserted, IRDY# deasserted).\nAn initiator may only perform back-to-back transactions when:\nAdditional timing constraints may come from the need to turn around are the target control lines, particularly DEVSEL#.\nThe target deasserts DEVSEL#, driving it high, in the cycle following the final data phase, which in the case of back-to-back transactions is the first cycle of the address phase.\nThe second cycle of the address phase is then reserved for DEVSEL# turnaround, so if the target is different from the prior one, it must not assert DEVSEL# until the third cycle (medium DEVSEL speed).\nOne case where this problem cannot arise is if the initiator knows somehow (presumably because the addresses share sufficient high-order bits) that the second transfer is addressed to the same target as the prior one.\nIn that case, it may perform back-to-back transactions.\nAll PCI targets must support this.\nIt is also possible for the target to keep track of the requirements.\nIf it never does fast DEVSEL, they are met trivially.\nIf it does, it must wait until medium DEVSEL time unless:\nTargets that have this ability indicate it by a special bit in a PCI configuration register, and if all targets on a bus have it, all initiators may use back-to-back transfers freely.\nA subtractive decoding bus bridge must know to expect this extra delay in the event of back-to-back cycles, to advertise back-to-back support.\n\n## 64-bit PCI\nStarting from revision 2.1, the PCI specification includes optional 64-bit support.\nThis is provided via an extended connector which provides the 64-bit bus extensions AD[63:32], C/BE[7:4]#, and PAR64, and a number of additional power and ground pins.\nThe 64-bit PCI connector can be distinguished from a 32-bit connector by the additional 64-bit segment.\nMemory transactions between 64-bit devices may use all 64 bits to double the data transfer rate.\nNon-memory transactions (including configuration and I/O space accesses) may not use the 64-bit extension.\nDuring a 64-bit burst, burst addressing works just as in a 32-bit transfer, but the address is incremented twice per data phase.\nThe starting address must be 64-bit aligned; i.e. AD2 must be 0.\nThe data corresponding to the intervening addresses (with AD2 = 1) is carried on the upper half of the AD bus.\nTo initiate a 64-bit transaction, the initiator drives the starting address on the AD bus and asserts REQ64# at the same time as FRAME#.\nIf the selected target can support a 64-bit transfer for this transaction, it replies by asserting ACK64# at the same time as DEVSEL#.\nA target may decide on a per-transaction basis whether to allow a 64-bit transfer.\nIf REQ64# is asserted during the address phase, the initiator also drives the high 32 bits of the address and a copy of the bus command on the high half of the bus.\nIf the address requires 64 bits, a dual address cycle is still required, but the high half of the bus carries the upper half of the address and the final command code during both address phase cycles; this allows a 64-bit target to see the entire address and begin responding earlier.\nIf the initiator sees DEVSEL# asserted without ACK64#, it performs 32-bit data phases.\nThe data which would have been transferred on the upper half of the bus during the first data phase is instead transferred during the second data phase.\nTypically, the initiator drives all 64 bits of data before seeing DEVSEL#.\nIf ACK64# is missing, it may cease driving the upper half of the data bus.\nThe REQ64# and ACK64# lines are held asserted for the entire transaction save the last data phase and deasserted at the same time as FRAME# and DEVSEL#, respectively.\nThe PAR64 line operates just like the PAR line, but provides even parity over AD[63:32] and C/BE[7:4]#.\nIt is only valid for address phases if REQ64# is asserted.\nPAR64 is only valid for data phases if both REQ64# and ACK64# are asserted.\n\n## Cache snooping (obsolete)\nPCI originally included optional support for [write-back](https://bliptext.com/articles/write-back) [cache coherence](https://bliptext.com/articles/cache-coherence).\nThis required support by cacheable memory targets, which would listen to two pins from the cache on the bus, SDONE (snoop done) and SBO# (snoop backoff).\nBecause this was rarely implemented in practice, it was deleted from revision 2.2 of the PCI specification, and the pins re-used for [SMBus](https://bliptext.com/articles/smbus) access in revision 2.3.\nThe cache would watch all memory accesses, without asserting DEVSEL#.\nIf it noticed an access that might be cached, it would drive SDONE low (snoop not done).\nA coherence-supporting target would avoid completing a data phase (asserting TRDY#) until it observed SDONE high.\nIn the case of a write to data that was clean in the cache, the cache would only have to invalidate its copy and would assert SDONE as soon as this was established.\nHowever, if the cache contained dirty data, the cache would have to write it back before the access could proceed.\nso it would assert SBO# when raising SDONE.\nThis would signal the active target to assert STOP# rather than TRDY#, causing the initiator to disconnect and retry the operation later.\nIn the meantime, the cache would arbitrate for the bus and write its data back to memory.\nTargets supporting cache coherency are also required to terminate bursts before they cross cache lines.\n\n# Development tools\nWhen developing and/or troubleshooting the PCI bus, examination of hardware signals can be very important.\n[Logic analyzers](https://bliptext.com/articles/logic-analyzers) and [bus analyzers](https://bliptext.com/articles/bus-analyzer) are tools that collect, analyze, and decode signals for users to view in useful ways.\n# [A PCI POST card that displays power-on self-test (POST) numbers during BIOS startup | upload.wikimedia.org/wikipedia/commons/f/f4/POST///card///98usd.jpg]","revisionCount":0},"hasMore":false,"nextCursor":null}