The AMD Family 10h, or K10, is a microprocessor microarchitecture by AMD based on the K8 microarchitecture. The first third-generation Opteron products for servers were launched on September 10, 2007, with the Phenom processors for desktops following and launching on November 11, 2007 as the immediate successors to the K8 series of processors (Athlon 64, Opteron, 64-bit Sempron).

Nomenclature

It appears that AMD has not used K-nomenclature (which originally stood for "Kryptonite" in the K5 processor ) from the time after the use of the codename K8 for the AMD K8 or Athlon 64 processor family, since no K-nomenclature naming convention beyond K8 has appeared in official AMD documents and press releases after the beginning of 2005. The name "K8L" was first coined by Charlie Demerjian in 2005, at the time a writer at The Inquirer, and was used by the wider IT community as a convenient shorthand while according to AMD official documents, the processor family was termed "AMD Next Generation Processor Technology". The microarchitecture has also been referred to as Stars, as the codenames for desktop line of processors was named under stars or constellations (the initial Phenom models being codenamed Agena and Toliman). In a video interview, Giuseppe Amato confirmed that the codename is K10. It was revealed, by The Inquirer itself, that the codename "K8L" referred to a low-power version of the K8 family, later named Turion 64, and that K10 was the official codename for the microarchitecture. AMD refers to it as Family 10h Processors, as it is the successor of the Family 0Fh Processors (codename K8). 10h and 0Fh refer to the main result of the CPUID x86 processor instruction. In hexadecimal numbering, 0Fh (h represents hexadecimal numbering) equals the decimal number 15, and 10h equals decimal 16. (The "K10h" form that sometimes pops up is an improper hybrid of the "K" code and Family identifier number.)

Schedule of launch and delivery

Timeline

Historical information

In 2003, AMD outlined the features for upcoming generations of microprocessors after the K8 family of processors in various events and analyst meetings, including the Microprocessor Forum 2003. The outlined features to be deployed by the next-generation microprocessors are as follows: In June 2006, AMD executive vice president Henri Richard had an interview with DigiTimes commented on the upcoming processor developments: "Q: What is your broad perspective on the development of AMD processor technology over the next three to four years? A: Well, as Dirk Meyer commented at our analysts meeting, we're not standing still. We've talked about the refresh of the current K8 architecture that will come in '07, with significant improvements in many different areas of the processor, including integer performance, floating point performance, memory bandwidth, interconnections and so on."

• AMD Executive Vice President, Henri Richard

<!-- ### Internal codenames As of November 2006, reports leaked the upcoming desktop part codenames Agena, Agena FX, and the core speeds of the parts range from 2.4 GHz - 2.9 GHz respectively, 512 [KB](https://bliptext.com/articles/kibibyte) L2 [cache](https://bliptext.com/articles/cpu-cache) each core, 2 [MB](https://bliptext.com/articles/mebibyte) L3 [cache](https://bliptext.com/articles/cpu-cache), using HyperTransport 3.0, with a TDP of 125 W. In recent reports, single core variants (codenamed Spica) and dual core with or without L3 [cache](https://bliptext.com/articles/cpu-cache) (codenamed Kuma and Rana respectively) are available under the same microarchitecture. During the AMD Analyst Day 2006 on December 14, 2006, AMD announced their official timeline for server, desktop and mobile processors. For the servers segment, AMD will unveil two new processors based on the architecture codenamed "Barcelona" and "Budapest" for 8/4/2-way and 1-way servers respectively. For the second half of 2007, [HyperTransport](https://bliptext.com/articles/hypertransport) 3.0 and [Socket AM2+](https://bliptext.com/articles/socket-am2) will be unveiled, which are designed for the specific implementation of the aforementioned consumer quad core desktop chip series, with naming convention changes from city names (up to middle of 2007) to stars or constellations after that, such as Agena; in addition, the [AMD Quad FX platform](https://bliptext.com/articles/amd-quad-fx-platform) and its immediate successor will support the high end enthusiast dual-processor versions of the chip, codenamed as Agena FX, updates the processors line for [AMD Quad FX platform](https://bliptext.com/articles/amd-quad-fx-platform). As with the server chips codenamed Barcelona, the new desktop quad core series will feature a shared L3 cache, 128-bit floating point (FP) units and an enhanced microarchitecture. Agena will be the native quad-core processor for the desktop. Kuma, a dual-core variant will follow on in Q3 while Rana, the dual-core version with no shared L3 cache is expected at the end of the year. ### Subsequent product launches More information about the upcoming chip codenamed "Montreal" on the server roadmap using [MCM](https://bliptext.com/articles/multi-chip-module) technique of two "Shanghai" cores with a total of 12 MB L3 cache codenamed [AMD K10.5](https://bliptext.com/articles/amd-k10-5). The desktop variant for Shanghai is codenamed Ridgeback. Afterwards is the release of products based on the [Bulldozer](https://bliptext.com/articles/bulldozer-processor) cores, which is optimized with integrated graphics core ([AMD Accelerated Processing Unit](https://bliptext.com/articles/amd-accelerated-processing-unit)) or native octal-core (8 core) server architecture (codenamed Sandtiger), and the [Bobcat](https://bliptext.com/articles/bobcat-processor) core, optimized for low-power operations. ### Change of model nomenclatures During Computex 2007 in early June, new information regarding the naming schemes of upcoming AMD microprocessors emerged. Additional letters indicating both performance and power envelope will precede the 4 digit model number. The model numbers of the new line of processors were apparently changed from the [PR ratings](https://bliptext.com/articles/pr-rating) used by its predecessors, the [Athlon 64](https://bliptext.com/articles/amd-k8) series processors (except [Phenom FX](https://bliptext.com/articles/amd-phenom-fx) series, being suggested to follow the nomenclature of [Athlon 64](https://bliptext.com/articles/amd-k8) FX series). As reported by DailyTech, the model numbers are in alpha-numeric format as AA-@### where AA are alphabetical letters, the first letter indicating the processor class and the second indicating the typical [TDP](https://bliptext.com/articles/thermal-design-power) power envelope. The character @ is the series indicator, which varies by branding (see below table), and the last three characters (###) are the model number, with higher numbers indicating greater performance. Not much information was known about the details of the model numbers, but the processors will be divided into three segments: Premium, Intermediate, and Value. Premium segment model numbers have processor class "G", Intermediate segment "B", and Value level "L", as discovered on the web from the AsRock website. Similarly, three levels of TDP, "more than 65W", "65W", and "less than 65W", are indicated by the letters "P", "S", and "E" respectively. As of November 2007, AMD has removed the letters from the model names and X2/X3/X4 monikers for depicting the number of cores of the processor, leaving just a four digit model number with the first character being the sole identification of the processor family, while Sempron remained using the LE prefix, as follows: ## Live demonstrations On November 30, 2006, AMD live demonstrated the native quad core chip known as "Barcelona" for the first time in public, while running Windows Server 2003 64-bit Edition. AMD claims 70% scaling of performance in real world loads, and better performance than [Intel](https://bliptext.com/articles/intel) [Xeon](https://bliptext.com/articles/xeon) 5355 processor codenamed Clovertown. On January 24, 2007, AMD Executive Vice President Randy Allen claimed that in live tests, in regard to a wide variety of workloads, "Barcelona" was able to demonstrate 40% performance advantage over the comparable Intel Xeon codenamed [Clovertown](https://bliptext.com/articles/clovertown-microprocessor) dual-processor (2P) quad-core processors. The expected performance of [floating point](https://bliptext.com/articles/floating-point) per core would be approximately 1.8 times that of the K8 family, at the same clock speed. On May 10, 2007, AMD held a private event demonstrating the upcoming processors codenamed Agena FX and chipsets, with one demonstrated system being [AMD Quad FX platform](https://bliptext.com/articles/amd-quad-fx-platform) with one [Radeon HD 2900 XT](https://bliptext.com/articles/radeon-r600) [graphics card](https://bliptext.com/articles/video-card) on the upcoming [RD790](https://bliptext.com/articles/rd700-chipset-series) chipset. The system was also demonstrated real-time converting a [720p](https://bliptext.com/articles/720p) video clip into another undisclosed format while all 8 cores were maxed at 100% by other tasks. ## Sister microarchitecture On the December 2006 analyst day, Executive vice president Marty Seyer announced a new mobile core codenamed [Griffin](https://bliptext.com/articles/griffin-processor) launched in 2008 with inherited power optimizations technologies from the K10 microarchitecture, but based on a K8 design. ### TLB bug In November 2007 AMD stopped delivery of Barcelona processors after a [bug](https://bliptext.com/articles/software-bug) in the [translation lookaside buffer](https://bliptext.com/articles/translation-lookaside-buffer) (TLB) of [stepping](https://bliptext.com/articles/stepping-version-numbers) B2 was discovered that could rarely lead to a [race condition](https://bliptext.com/articles/race-condition) and thus a system lockup. A patch in [BIOS](https://bliptext.com/articles/bios) or software worked around the bug by disabling cache for page tables, but it was connected to a 5 to 20% performance penalty. Kernel [patches](https://bliptext.com/articles/patch-computing) that would almost completely avoid this penalty were published for [Linux](https://bliptext.com/articles/linux). In April 2008, the new stepping B3 was brought to the market by AMD, including a fix for the bug plus other minor enhancements. # Features ## Fabrication technology AMD has introduced the microprocessors manufactured at [65 nm](https://bliptext.com/articles/65-nm) feature width using [Silicon-on-insulator (SOI)](https://bliptext.com/articles/silicon-on-insulator) technology, since the release of K10 coincides with the volume ramp of this manufacturing process. ## Supported DRAM standards The [K8](https://bliptext.com/articles/amd-k8) family was known to be particularly sensitive to memory latency since its design gains performance by minimizing this through the use of an on-die [memory controller](https://bliptext.com/articles/memory-controller) (integrated into the CPU); increased latency in the external modules negates the usefulness of the feature. [DDR2 RAM](https://bliptext.com/articles/ddr2-sdram) introduces some additional latency over [DDR RAM](https://bliptext.com/articles/ddr-sdram) since the [DRAM](https://bliptext.com/articles/dynamic-random-access-memory) is internally driven by a clock at one quarter of the external data frequency, as opposed to one half that of DDR. However, since the command clock rate in DDR2 is doubled relative to DDR and other latency-reducing features (e.g. additive latency) have been introduced, common comparisons based on [CAS latency](https://bliptext.com/articles/cas-latency) alone are not sufficient. For example, [Socket AM2](https://bliptext.com/articles/socket-am2) processors are known to demonstrate similar performance using DDR2 SDRAM as [Socket 939](https://bliptext.com/articles/socket-939) processors that utilize DDR-400 SDRAM. K10 processors support [DDR2 SDRAM](https://bliptext.com/articles/ddr2-sdram) rated up to DDR2-1066 (1066 MHz). While some desktop K10 processors are AM2+ supporting only DDR2, an AM3 K10 processor supports both DDR2 and DDR3. A few AM3 motherboards have both DDR2 and DDR3 slots (this does not mean that both types can be fitted at the same time), but for the most part they have only DDR3. Lynx desktop processors only support DDR3, as they use the FM1 socket. # Microarchitecture characteristics Characteristics of the microarchitecture include the following: # [K10 architecture | upload.wikimedia.org/wikipedia/commons/d/d6/AMD///K10///Arch.svg] # [K10 single core with overlay description, excluding the L2 cache array | upload.wikimedia.org/wikipedia/commons/2/27/K10h.jpg] # Feature tables ## CPUs ## APUs [APU features table](https://bliptext.com/articles/template-amd-apu-features) # Desktop ## Phenom models ### Agena (65 nm SOI, quad-core) ### Toliman (65 nm SOI, tri-core) ## Phenom II models ### Thuban (45 nm SOI, hexa-core) ### Zosma (45 nm SOI, quad-core) ### Deneb (45 nm SOI, quad-core) ### 42 TWKR Limited Edition (45 nm SOI, quad-core) AMD released a limited edition Deneb-based processor to extreme [overclockers](https://bliptext.com/articles/overclocking) and partners. Fewer than 100 were manufactured. The "42" officially represents four cores running at 2 GHz, but is also a reference to [the answer to life, the universe, and everything](https://bliptext.com/articles/the-answer-to-life-the-universe-and-everything) from [The Hitchhiker's Guide to the Galaxy](https://bliptext.com/articles/the-hitchhiker-s-guide-to-the-galaxy). ### Propus (45 nm SOI, quad-core) ### Heka (45 nm SOI, tri-core) ### Callisto (45 nm SOI, dual-core) ### Regor (45 nm SOI, dual-core) ## Athlon X2 models ### Kuma (65 nm SOI, dual-core) ### Regor/Deneb (45 nm SOI, dual-core) ## Athlon II Models ### Zosma (45 nm SOI, quad-core) ### Propus (45 nm SOI, quad-core) ### Rana (45 nm SOI, tri-core) ### Regor (45 nm SOI, dual-core) ### Sargas (45 nm SOI, single-core) ### Lynx (32 nm SOI, dual or quad-core) ## Sempron models ### Sargas (45 nm SOI, single-core) ## Sempron X2 models ### Regor (45 nm SOI, dual-core) ### Lynx (32 nm SOI, dual-core) ## Llano "APUs" ### Lynx (32 nm SOI, dual or quad-core) The first generation desktop APUs based on the K10 microarchitecture were released in 2011 (some models do not provide graphics capability, such as the Lynx Athlon II and Sempron X2). # Mobile ## Turion II (Ultra) models ### "Caspian" (45nm SOI, dual-core) ## Turion II models ### "Caspian" (45nm SOI, dual-core) ### "Champlain" (45nm SOI, dual-core) ## Athlon II models ### "Caspian" (45nm SOI, dual-core) ### "Champlain" (45nm SOI, dual-core) ## Sempron models ### "Caspian" (45nm SOI, single-core) ## Turion II Neo models ### "Geneva" (45nm SOI, dual-core) ## Athlon II Neo models ### "Geneva" (45nm SOI, dual-core) ### "Geneva" (45nm SOI, single-core) ## V models ### "Geneva" (45nm SOI, single-core) ### "Champlain" (45nm SOI, single-core) ## Phenom II models ### "Champlain" (45nm SOI, quad-core) ### "Champlain" (45nm SOI, tri-core) ### "Champlain" (45nm SOI, dual-core) ## Llano APUs ### "Sabine" (32nm SOI, dual or quad-core) # Server There are two generations of K10-based processors for servers: Opteron [65 nm](https://bliptext.com/articles/opteron) and [45 nm](https://bliptext.com/articles/opteron). # Successor AMD discontinued further development of K10 based CPUs after Thuban, choosing to focus on [Fusion](https://bliptext.com/articles/amd-fusion) products for mainstream desktops and laptops and [Bulldozer](https://bliptext.com/articles/bulldozer-microarchitecture) based products for the performance market. However, within the Fusion product family, [APUs](https://bliptext.com/articles/amd-accelerated-processing-unit) such as the first generation A4, A6 and A8-series chips (Llano [APUs](https://bliptext.com/articles/amd-accelerated-processing-unit)) continued to use K10-derived CPU cores in conjunction with a Radeon graphics core. K10 and its derivatives were phased out of production by the introduction of Trinity-based APUs in 2012, which replaced the K10 cores in the APU with Bulldozer-derived cores. # Family 11h and 12h derivatives ## Turion X2 Ultra Family 11h The Family 11h microarchitecture was a mixture of both K8 and K10 designs with lower power consumption for laptop that was marketed as Turion X2 Ultra and was later replaced by completely K10-based designs. ## Fusion Family 12h The Family 12h microarchitecture is a derivative of the K10 design: # Media discussions Note: These media discussions are listed in ascending date of publication.